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22.13 Cautions
(1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation.
(2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte).
(3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.
Use the RETB instruction.
(4) The RETCS instruction must not be used to return from a software interrupt caused by a BRKCS instruction.
Use the RETCSB instruction.
(5) When a maskable interrupt is acknowledged by vectored interruption, the RETI instruction must be used to return
from the interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction
is used.
(6) The RETCS instruction must be used to return from a context switching interrupt. Subsequent interrupt related
operations will not be performed normally if a different instruction is used.
(7) Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt
service program. If you do not want macro service processing to be performed during a non-maskable interrupt
service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program
to prevent macro service generation.
(8) The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledg-
ment will not be performed normally if a different instruction is used. Refer to 22.12 Restoring Interrupt Function
to Initial State when a program is to be restarted from the initial status after a non-maskable interrupt
acknowledgement.
(9) Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program
execution (except when a high non-maskable interrupt request is generated during execution of a low-priority
non-maskable interrupt service program) and for a certain period after execution of the special instructions shown
in 22.9. Therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is
undefined, in particular after reset release, etc. In this case, depending on the value of the SP, it may happen
that the program counter (PC) and program status word (PSW) are written to the address of a write-inhibited
special function register (SFR) (refer to Table 3-6 in 3.9 Special Function Registers (SFRs)), and the CPU
becomes deadlocked, or an unexpected signal output from a pin, or PC and PSW are written to an address is
which RAM is not mounted, with the result that the return from the non-maskable interrupt service program is
not performed normally and a software upset occurs.
Therefore, the program following RESET release must be as follows.
CSEG AT 0
DW
STRT
CSEG BASE
STRT:
LOCATION 0FH; or LOCATION 0
MOVG SP, #imm24
436
CHAPTER 22 INTERRUPT FUNCTIONS
User's Manual U12697EJ3V0UM
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