NEC mPD784225 Series User Manual page 491

IDLE Mode Setting
Item
Clock generator
CPU
Port (output latch)
16-bit timer/event counter
8-bit timer/event counters 1, 2
8-bit timers 5 and 6
Watch timer
Watchdog timer
A/D converter
D/A converter
Real-time output port
2
Serial interface Except I C bus
mode
2
I C bus mode
External interrupt INTP0 to INTP5 Operation enabled
Bus lines during AD0 to AD7
external expansion A8 to A19
ASTB
WR, RD
WAIT
Caution In the IDLE mode, only external interrupts (INTP0 to INTP5) and watch timer interrupts (INTWT)
can release the IDLE mode and be acknowledged as interrupt requests. All other interrupt
requests are pended, and acknowledged after the IDLE mode has been released through NMI
input, INTP0 to INTP5 input or INTWT.
CHAPTER 24 STANDBY FUNCTION
Table 24-7. Operating States in IDLE Mode
With Subsystem Clock
The oscillation circuits in both the main system clock and subsystem clock continue
operating. The clock supply to both the CPU and peripherals is stopped.
Operation disabled
Holds the state before the IDLE mode was set.
Operational when the watch timer output
is selected as the count clock (Select f
as the count clock of the watch timer.)
Operational only when TI1 and TI2 are selected as the count clocks
Operational only when TI5 and TI6 are selected as the count clocks
Operational only when f is selected as
XT
the count clock
Operation disabled
Operation disabled
Operation enabled
Operational when an external trigger is used or TI1 and TI2 are selected as the count
clocks of the 8-bit timer/event counters 1 and 2
Operational only when an external input clock is selected as the serial clock
Operation disabled
High impedance
High impedance
High impedance
High impedance
Holds input status
User's Manual U12697EJ3V0UM
Without Subsystem Clock
Operation disabled
XT
Operation disabled
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