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CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 16-5. Format of Baud Rate Generator Control Registers 1 and 2 (BRGC1, BRGC2)
Address: 0FF76H, 0FF77H After reset: 00H
Symbol
7
BRGCn
0
TPSn2
TPSn2
MDLn3
Cautions 1. If a write operation to BRGCn is performed during communication, the baud rate
generator output will become garbled and normal communication will not be achieved.
Consequently, do not write in BRGCn during communications.
2. Refer to the data sheet for details of the high-/low-level width of ASCKn when selecting
the external clock (ASCKn) for the source clock of the 5-bit counter.
Remarks 1. n = 1, 2
2. Figures in parentheses apply to operation at f
3. f
: Source clock of 5-bit counter
SCK
4. k: Value set in MDLn0 to MDLn3 (0 ≤ k ≤ 14)
R/W
6
5
4
TPSn1
TPSn0
TPSn1
TPSn0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MDLn2
MDLn1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
User's Manual U12697EJ3V0UM
3
2
MDLn3
MDLn2
MDLn1
5-bit counter source clock selection
External clock (ASCKn)
f
(12.5 MHz)
XX
f
/2 (6.5 MHz)
XX
f
/4 (3.13 MHz)
XX
f
/8 (1.56 MHz)
XX
f
/16 (781 kHz)
XX
f
/32 (391 kHz)
XX
TO1 (TM1 output)
Baud rate generator
TPSn0
input clock selection
0
f
/16
SCK
1
f
/17
SCK
0
f
/18
SCK
1
f
/19
SCK
0
f
/20
SCK
1
f
/21
SCK
0
f
/22
SCK
1
f
/23
SCK
0
f
/24
SCK
1
f
/25
SCK
0
f
/26
SCK
1
f
/27
SCK
0
f
/28
SCK
1
f
/29
SCK
0
f
/30
SCK
1
Setting prohibited
= 12.5 MHz
XX
1
0
MDLn0
k
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
–
267
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