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Figure No.
13-7
A/D Conversion Operation by Software Start ...................................................................................
13-8
Overall Error ......................................................................................................................................
13-9
Quantization Error .............................................................................................................................
13-10
Zero-Scale Error ...............................................................................................................................
13-11
Full-Scale Error .................................................................................................................................
13-12
Integral Linearity Error ......................................................................................................................
13-13
Differential Linearity Error .................................................................................................................
13-14
Method to Reduce Current Consumption in Standby Mode .............................................................
13-15
Handling of Analog Input Pin ............................................................................................................
13-16
A/D Conversion End Interrupt Request Generation Timing ..............................................................
13-17
Conversion Results Immediately After A/D Conversion Is Started ...................................................
13-18
Conversion Result Read Timing (When Conversion Result Is Undefined) .......................................
13-19
Conversion Result Read Timing (When Conversion Result Is Normal) ............................................
13-20
Example of Capacitor Connection Between V
13-21
Internal Equivalence Circuit of ANI0 to ANI7 Pins ............................................................................
13-22
Example of Circuit When Signal Source Impedance Is High ............................................................
14-1
Block Diagram of D/A Converter .......................................................................................................
14-2
Format of D/A Converter Mode Registers 0 and 1 (DAM0, DAM1) ..................................................
14-3
Buffer Amp Insertion Example ..........................................................................................................
15-1
Serial Interface Example ...................................................................................................................
16-1
Switching Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ...................................
16-2
Block Diagram in Asynchronous Serial Interface Mode ....................................................................
16-3
Format of Asynchronous Serial Interface Mode Registers 1 and 2 (ASIM1, ASIM2) ........................
16-4
Format of the Asynchronous Serial Interface Status Registers 1 and 2 (ASIS1, ASIS2) ..................
16-5
Format of Baud Rate Generator Control Registers 1 and 2 (BRGC1, BRGC2) ...............................
16-6
Baud Rate Allowable Error Considering Sampling Errors (When k = 0) ...........................................
16-7
Format of Asynchronous Serial Interface Transmit/Receive Data ....................................................
16-8
Asynchronous Serial Interface Transmit Completion Interrupt Request Timing ...............................
16-9
Asynchronous Serial Interface Receive Completion Interrupt Request Timing ................................
16-10
Receive Error Timing ........................................................................................................................
16-11
Block Diagram in 3-Wire Serial I/O Mode .........................................................................................
16-12
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
16-13
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
16-14
Format of Serial Operation Mode Registers 1 and 2 (CSIM1, CSIM2) .............................................
16-15
3-Wire Serial I/O Mode Timing ..........................................................................................................
17-1
Block Diagram of Clocked Serial Interface (in 3-Wire Serial I/O Mode) ...........................................
17-2
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
17-3
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
17-4
Format of Serial Operation Mode Register 0 (CSIM0) ......................................................................
LIST OF FIGURES (4/8)
Title
and AV
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DD0
DD
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