NEC mPD784225 Series User Manual page 274

16-/8-bit single-chip microcontrollers

Table of Contents

CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

• Baud rate capacity error range

The baud rate capacity range depends on the number of bits per frame and the counter division ratio

[1/(16 + k)].

Table 16-3 shows the relationship between the main system clock and the baud rate, Table 16-6

shows a baud rate allowable error example.

Table 16-3. Relationship Between Main System Clock and Baud Rate

Remark When TM1 output is used, 150 to 38400 bps is supported (during operation at f

Figure 16-6. Baud Rate Allowable Error Considering Sampling Errors (When k = 0)

Reference timing

(Clock period T)

High-speed clock for which

normal reception is enabled

(Clock period T')

Low-speed clock for which

normal reception is enabled

(Clock period T'')

Remark T: 5-bit counter source clock period

Baud rate allowable error (k = 0)

User's Manual U12697EJ3V0UM

× 100 = 4.8438 (%)

Sampling error