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CHAPTER 18 I
18.5.6 Wait signal (WAIT)
The wait signal notifies the other side that the master or slave is being prepared (wait state) for data communication.
The wait state is notified to the other side by setting the SCL0 pin low. When both the master and the slave are
released from the wait state, the next transfer can start.
(1) The master has a 9 clock wait, and the slave has an 8 clock wait
Master
IIC0
SCL0
6
Slave
IIC0
SCL0
ACKE0
H
Transfer lines
SCL0
6
SDA0
D2
C BUS MODE ( µ PD784225Y SUBSERIES ONLY)
2
Figure 18-13. Wait Signal (1/2)
(Master: transmission, Slave: receiving, ACKE0 = 1)
The master returns to Hi-Z,
but the slave waits (low level).
7
8
9
Wait after the eighth
clock is output.
7
8
D1
D0
User's Manual U12697EJ3V0UM
Wait after the ninth
clock is output.
IIC0 ← FFH or WREL0 ← 1
9
ACK
IIC0 ← data (wait release)
1
2
3
1
2
3
D7
D6
D5
313
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