Gpio, Connector J5; System Management Bus (Smbus) - Xilinx ML310 User Manual

Board Hardware

GPIO, connector J5

System Management Bus (SMBus)

ML310 User Guide
UG068 (v1.01) August 25, 2004
All manuals and user guides at all-guides.com
There are 15 GPIO pins connecting the ALi M1535D+ to the J5 24 pin header. These may be
accessed via the ALi M1535D+ via the PCI Bus. Please review the ALi M1535D+ Data
sheets for more detailed information.
Table 2-17 shows the types and number of GPIO signals available to the user from the ALi
South Bridge.
Table 2-17: Type of GPIO Available on Header J5
ALi GPIO Types
Output 5
Input 4
Input/Output 6
Table 2-18 shows the connections from the ALi, M1535D+, GPIO signals available at the
GPIO header (J5). Please review the ALi M1535D+ Data sheets, located on the ML310
CDROM, for more detailed information.
Table 2-18: GPIO Connections on Header J5
GPIO Header
Schem Net Name
GPO_35 24
GPO_34 22
GPO_30 20
GPO_29 23
GPO_10 21
GPI_36 7
GPI_34 5
GPI_25 3
GPI_24 1
GPIO_3 15
GPIO_23 19
GPIO_22 17
GPIO_2 13
GPIO_1 11
GPIO_0 9
The System Management Bus (SMBus) host controller in the M1535D+ supports the ability
to communicate with power related devices using the SMBus protocol. It provides quick
Number
Available
M1535D+
(J5) (U15)
P19
P18
N18
N17
T3
U8
W7
E9
M17
Y4
U5
U6
W4
V4
Y3
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IO Type
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
R
45