Agilent Technologies 8711C Service Manual page 132

Test Test Name
Number
*1 680x0 Processor
*2 BootROM Checksum
*3 Main ROM Checksum
*4 DR M
*5 (Not used)
*6 340x0 GSP Processor
*7 GSP Video
8 (Not used)
*9 320C32 Program SR M
*10 320C32 DSP Processor
11 68030 and 320C32 Communication Not implemented.
*12 Backplane Bus
*13 Non-volatile SR M
*14 L N
15 CPU Support Circuitry
16 nalog Bus
17 Real Time Clock
*18 Front Panel Interface
*19 Floppy Disk Controller
*20 HP-IB Interface
*21 RS-232 Interface
*22 DIN Keyboard Interface
*23 Centronics Interface
* Denotes a test run during power-up.
Table 5-1. Analyzer Self-Tests
Executes internal tests of 68030 main CPU and 68882 coprocessor.
Checks all registers. Checks logic, math, shift/rotate, and bit
manipulation instructions.
Checksum of bootROM to verify bootROM rmware code.
Checksum of ash EPROM to check main rmware.
Writes a series of test patterns to the DR M and reads them back.
Checks size of DR M.
Not implemented.
Not implemented.
This test number is not used because the test status LED powers up
with the number \8" as the default. If there is a problem with the
68030 CPU, this \8" will remain displayed on the LED. Check power
supplies. If good, then replace CPU board.
Checks the program SR M used by the TMS 320C32 digital signal
processor.
Tests the TMS 320C32 digital signal processor.
Tests the ability of the 68030 to access the other boards through the
backplane assembly.
Tests the integrity of the contents of battery-backed SR M. Detects
loss of power to the SR M.
Tests the operation of the L N circuitry.
Tests various circuits that are required for the main processor (68030)
to operate. Tests timers and interrupts. ttempts to clear and disable
all interrupts. Tests each interrupt signal to the 68030 to make sure
that none of them are asserted.
Tests the analog bus control circuitry and +5V and EPROM Vpp on the
CPU board.
Tests the real time clock and tries to access registers on the chip.
Tests the front panel control processor. Tries to access registers on the
chip.
Tests the 3.5" internal disk controller portion of the Super I/O chip.
Tries to access registers on the chip. Writes commands to the chip,
and veri es correct response. lso steps the oppy disk drive's head
from track 0 to 9, and back to 0, to test the ability to nd track 0.
Tests the HP-IB interface circuitry. Tries to access registers on the
chip. Writes commands to the chip, and veri es correct response.
Tests the RS-232 portion of the Super I/O chip. Tries to access registers
on the chip. Checks for missing clock input to the chip.
Tests the DIN keyboard control portion of the Super I/O. Tries to
access registers on the chip.
Tests the Centronics interface portion of the Super I/O.
escription
Serv ce Related Menus 5-3