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Figure No.
6-8
CR0m Capture Operation with Rising Edge Specified .....................................................................
6-9
Pulse Width Measurement Operation Timing by Free-Running Counter
(with Both Edges Specified) ..............................................................................................................
6-10
16-Bit Timer Register Start Timing ....................................................................................................
6-11
Capture Register Data Retention Timing ..........................................................................................
7-1
8-Bit Timer 1 TM1 Block Diagram .....................................................................................................
7-2
Timer Clock Select Register 1 (TCL1) Format ..................................................................................
7-3
8-Bit Timer Mode Control Register 1 (TMC1) Format .......................................................................
7-4
Interval Timer Operation Timings ......................................................................................................
7-5
8-Bit Timer 1 (TM1) Start Timing .......................................................................................................
7-6
Timing after Compare Register Change during Timer Count Operation ...........................................
8-1
8-Bit Timer/Event Counter 2 TM2 Block Diagram .............................................................................
8-2
8-Bit Timer/Event Counter 3 TM3 Block Diagram .............................................................................
8-3
Timer Clock Select Register 2 (TCL2) Format ..................................................................................
8-4
Timer Clock Select Register 3 (TCL3) Format ..................................................................................
8-5
8-Bit Timer Mode Control Registers 2 and 3 (TMC2 and TMC3) Format .........................................
8-6
Port Mode Register 4 (PM4) Format .................................................................................................
8-7
Interval Timer Operation Timings ......................................................................................................
8-8
External Event Counter Operation Timings (with Rising Edge Specified) ........................................
8-9
PWM Output Operation Timing .........................................................................................................
8-10
Operation Timing by Change of CRn ................................................................................................
8-11
8-Bit Counters 2 and 3 (TM2 and TM3) Start Timing ........................................................................
8-12
Timing after Compare Register Change during Timer Count Operation ...........................................
9-1
Watch Timer Block Diagram .............................................................................................................
9-2
Watch Timer Mode Control Register (WTM) Format ........................................................................
9-3
Watch Timer/Interval Timer Operation Timing ...................................................................................
10-1
Watchdog Timer Block Diagram .......................................................................................................
10-2
Watchdog Timer Clock Select Register (WDCS) Format ..................................................................
10-3
Watchdog Timer Mode Register (WDTM) Format ............................................................................
11-1
Clock Output Controller Block Diagram ............................................................................................
11-2
Clock Output Selection Register (CKS) Format ................................................................................
11-3
Port Mode Register 6 (PM6) Format .................................................................................................
11-4
Remote Control Output Application Example ...................................................................................
12-1
A/D Converter Block Diagram ...........................................................................................................
12-2
Power-Fail Detection Function Block Diagram .................................................................................
12-3
A/D Converter Mode Register (ADM1) Format .................................................................................
12-4
Analog Input Channel Specification Register (ADS1) Format ..........................................................
12-5
Power-Fail Compare Mode Register (PFM) Format .........................................................................
20
LIST OF FIGURES (2/5)
Title
Preliminary User's Manual U14581EJ3V0UM00
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