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(4) Occurrence of INTTM0n
INTTM0n occurs even if no capture pulse exists, immediately after the timer operation has been started (TMC02
of TMC0 has been set to 1) with a high level applied to input pins TI00 to TI02 of 16-bit timer 0, and with the
rising edge (with ESn1 and ESn0 of PRM0 set to 0, 1), or both the rising and falling edges (with ESn1 and ESn0
of PRM0 set to 1, 1) selected. However, INTTM0n does not occur if a low level is applied to TI00 to TI02.
Remark n = 0 to 2
112
CHAPTER 6 16-BIT TIMER 0 TM0
Preliminary User's Manual U14581EJ3V0UM00
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