Multiple Interrupt Servicing - NEC mPD780852 Series Preliminary User's Manual

8-bit single-chip microcontrollers
Table of Contents

Advertisement

19.4.4 Multiple interrupt servicing

Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except
non-maskable interrupts). Also, when an interrupt request is received, interrupt requests acknowledge becomes
disabled (IE = 0). Therefore, to enable multiple interrupts, it is necessary to set the IE flag (to 1) with the EI instruction
during interrupt servicing to enable interrupt acknowledge.
Moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupts.
In the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower
than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for
multiple interrupt servicing.
Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held
pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following
execution of one main processing instruction execution.
Multiple interrupt servicing is not possible during non-maskable interrupt servicing.
Table 19-4 shows interrupt requests enabled for multiple interrupt servicing, and Figure 19-14 shows multiple
interrupt examples.
Table 19-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Multiple Interrupt Request
Interrupt Being Serviced
Non-maskable interrupt
Maskable interrupt
ISP = 0
ISP = 1
Software interrupt
Remarks 1.
: Multiple interrupt enable
2. ×: Multiple interrupt disable
3. ISP and IE are flags contained in PSW.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being
serviced.
IE = 0: Interrupt request acknowledge is disabled.
IE = 1: Interrupt request acknowledge is enabled.
4. ××PR is a flag contained in PR0L, PR0H, PR1L, and PR1H.
××PR = 0:
××PR = 1:
258
CHAPTER 19 INTERRUPT FUNCTIONS
Non-Maskable Interrupt Request
×
Higher priority level
Lower priority level
Preliminary User's Manual U14581EJ3V0UM00
Maskable Interrupt Request
××PR = 0
IE = 1
IE = 0
IE = 1
×
×
×
×
×
×
×
××PR = 1
IE = 0
×
×
×
×

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mpd780851Mpd780851aMpd780852aMpd78f0852

Table of Contents