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Figure No.
12-6
Power-Fail Compare Threshold Value Register (PFT) Format .........................................................
12-7
Basic Operation of 8-Bit A/D Converter ............................................................................................
12-8
Relation between Analog Input Voltage and A/D Conversion Result ................................................
12-9
A/D Conversion .................................................................................................................................
12-10
Example of Method of Reducing Current Consumption in Standby Mode .......................................
12-11
Analog Input Pin Connection ............................................................................................................
12-12
A/D Conversion End Interrupt Request Generation Timing ..............................................................
12-13
D/A Converter Mode Register (DAM1) Format .................................................................................
13-1
Serial Interface UART Block Diagram ...............................................................................................
13-2
Asynchronous Serial Interface Mode Register (ASIM) Format .........................................................
13-3
Asynchronous Serial Interface Status Register (ASIS) Format ........................................................
13-4
Baud Rate Generator Control Register (BRGC) Format ..................................................................
13-5
Error Tolerance (When k = 0) Including Sampling Errors .................................................................
13-6
Format of Transmit/Receive Data in Asynchronous Serial Interface ................................................
13-7
Asynchronous Serial Interface Transmit Completion Interrupt Timing ..............................................
13-8
Asynchronous Serial Interface Receive Completion Interrupt Timing ...............................................
13-9
Receive Error Timing ........................................................................................................................
14-1
Serial Interface SIO2 Block Diagram ................................................................................................
14-2
Serial Operation Mode Register 2 (CSIM2) Format ..........................................................................
14-3
Serial Transfer Operation Timing According to CLPO and CLPH Settings .......................................
14-4
Serial Receive Data Buffer Status Register (SRBS2) Format ..........................................................
14-5
Port Mode Register 0 (PM0) Format .................................................................................................
14-6
Operation Timing When CLPH Is Set to 0 (Serial output data: 55H, serial input data: AAH) .........
14-7
Operation Timing When CLPH Is Set to 1 (Serial output data: 55H, serial input data: AAH) .........
14-8
Receive Operation ............................................................................................................................
15-1
Serial Interface SIO3 Block Diagram ................................................................................................
15-2
Serial Operation Mode Register 3 (CSIM3) Format ..........................................................................
15-3
3-Wire Serial I/O Mode Timing ..........................................................................................................
16-1
LCD Controller/Driver Block Diagram ...............................................................................................
16-2
LCD Clock Selector Block Diagram ..................................................................................................
16-3
LCD Display Mode Register (LCDM) Format ...................................................................................
16-4
LCD Display Control Register (LCDC) Format .................................................................................
16-5
Relation between LCD Display Data Memory Contents and Segment/Common Outputs ...............
16-6
Common Signal Waveform ...............................................................................................................
16-7
Common Signal and Segment Signal Voltages and Phases ............................................................
16-8
Example of Connection of LCD Drive Power Supply ........................................................................
16-9
4-Time-Division LCD Display Pattern and Electrode Connections ...................................................
16-10
4-Time-Division LCD Panel Connection Example ............................................................................
16-11
4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...............................................
16-12
LCD Timer Control Register (LCDTM) Format .................................................................................
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Title
Preliminary User's Manual U14581EJ3V0UM00
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