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Figure No.
17-1
Sound Generator Block Diagram ......................................................................................................
17-2
Concept of Basic Cycle Output Signal SGO .....................................................................................
17-3
Sound Generator Control Register (SGCR) Format .........................................................................
17-4
Sound Generator Buzzer Control Register (SGBR) Format .............................................................
17-5
Sound Generator Amplitude Register (SGAM) Format .....................................................................
17-6
Sound Generator Output Operation Timing ......................................................................................
18-1
Meter Controller/Driver Block Diagram .............................................................................................
18-2
1-Bit Addition Circuit Block Diagram .................................................................................................
18-3
Timer Mode Control Register (MCNTC) Format ...............................................................................
18-4
Compare Control Register n (MCMPCn) Format ..............................................................................
18-5
Port Mode Control Register (PMC) Format ......................................................................................
18-6
Restart Timing after Count Stop (Count Start→Count Stop→Count Start) ......................................
18-7
Timing in 1-Bit Addition Circuit Operation .........................................................................................
18-8
Timing of Output with 1 Clock Shifted ...............................................................................................
19-1
Basic Configuration of Interrupt Function .........................................................................................
19-2
Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format ..............................................................
19-3
Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format ............................................................
19-4
Priority Specify Flag Register (PR0L, PR0H, PR1L) Format ............................................................
19-5
External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) Format .......................................................
19-6
Prescaler Mode Register (PRM0) Format ........................................................................................
19-7
Program Status Word Format ...........................................................................................................
19-8
Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................
19-9
Non-Maskable Interrupt Request Acknowledge Timing ....................................................................
19-10
Non-Maskable Interrupt Request Acknowledge Operation ...............................................................
19-11
Interrupt Request Acknowledge Processing Algorithm .....................................................................
19-12
Interrupt Request Acknowledge Timing (Minimum Time) .................................................................
19-13
Interrupt Request Acknowledge Timing (Maximum Time) ................................................................
19-14
Multiple Interrupt Examples ..............................................................................................................
19-15
Interrupt Request Hold ......................................................................................................................
20-1
Oscillation Stabilization Time Select Register (OSTS) Format .........................................................
20-2
HALT Mode Clear upon Interrupt Generation ...................................................................................
20-3
HALT Mode Clear upon RESET Input ..............................................................................................
20-4
STOP Mode Clear upon Interrupt Generation ..................................................................................
20-5
STOP Mode Clear upon RESET Input ..............................................................................................
21-1
Reset Function Block Diagram .........................................................................................................
21-2
Timing of Reset by RESET Input ......................................................................................................
21-3
Timing of Reset due to Watchdog Timer Overflow ...........................................................................
21-4
Timing of Reset in STOP Mode by RESET Input ..............................................................................
22
LIST OF FIGURES (4/5)
Title
Preliminary User's Manual U14581EJ3V0UM00
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