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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3
8.2 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Configurations
The 8-bit timer/event counters 2 TM2 and 3 TM3 consist of the following hardware.
Table 8-1. 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Configurations
Timer register
Register
Timer output
Control register
(1) 8-bit counters 2, 3 (TM2, TM3)
TMn is an 8-bit read-only register which counts the count pulses.
The counter is incremented in synchronization with the rising edge of the count clock. When count value is read
during operation, count clock input is temporary stopped, and then the count value is read. In the following
situations, the count value is set to 00H.
<1> RESET input
<2> Clear TCE2 and TCE3
<3> Match between TM2 and TM3 and CR2 and CR3 in clear and start mode with match between TM2 and
TM3 and CR2 and CR3
(2) 8-bit compare registers 2, 3 (CR2, CR3)
The value set in the CR2 is constantly compared with the 8-bit counter 2 (TM2) count value and the value set
in the CR3 is constantly compared with the 8-bit counter 3 (TM3) count value, and interrupt requests (INTTM2
and INTTM3) are generated if they match (except PWM mode).
CR2 and CR3 are set with an 8-bit memory manipulation instruction. They are not set with a 16-bit memory
manipulation instruction.
It is possible to rewrite the values of CR2 and CR3 within 00H to FFH during count operation.
RESET input clears these regiters to 00H.
Item
8-bit counter × 2 (TM2, TM3)
8-bit compare register × 2 (CR2, CR3)
2 (TIO2, TIO3)
Timer clock select registers 2, 3 (TCL2, TCL3)
8-bit timer mode control registers 2, 3 (TMC2, TMC3)
Port mode register 4 (PM4)
Preliminary User's Manual U14581EJ3V0UM00
Configuration
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