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19.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask
(MK) flag corresponding to that interrupt is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt
enable state (when IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing
of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table
19-3 below.
For the interrupt request acknowledge timing, see the Figures 19-12 and 19-13.
Table 19-3. Times from Generation of Maskable Interrupt Request until Servicing
When ××PR× = 0
When ××PR× = 1
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock: 1/f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specify flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19-11 shows the interrupt request acknowledge algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of program
status word (PSW), then program counter (PC), the IE flag is reset (to 0), and the contents of the priority specify flag
corresponding to the acknowledged interrupt are transferred to the ISP flag. Further, the vector table data determined
for each interrupt request is loaded into PC and branched.
Return from an interrupt is possible with the RETI instruction.
CHAPTER 19 INTERRUPT FUNCTIONS
Minimum Time
7 clocks
8 clocks
(f
: CPU clock)
CPU
Preliminary User's Manual U14581EJ3V0UM00
Note
Maximum Time
32 clocks
33 clocks
255
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