NEC mPD780852 Series Preliminary User's Manual page 274

8-bit timer TM1 to TM3
Watch timer
Watchdog timer
Clock output controller
A/D converter
Serial interface UART
Serial interface SIO2
Serial interface SIO3
LCD controller/driver
Sound generator
Meter controller/driver
Interrupt
274
CHAPTER 21 RESET FUNCTION
Table 21-1. Hardware Status after Reset (2/2)
Hardware
Timer counters (TM1 to TM3)
Compare registers (CR1 to CR3)
Clock select registers (TCL1 to TCL3)
Mode control registers (TMC1 to TMC3)
Mode control register (WTM)
Clock select register (WDCS)
Mode register (WDTM)
Clock output selection register (CKS)
Mode register (ADM1)
Conversion result register (ADCR1)
Analog input channel specification register (ADS1)
Power-fail compare mode register (PFM)
Power-fail compare threshold value register (PFT)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
Transmit shift register (TXS)
Receive buffer register (RXB)
Operation mode register 2 (CSIM2)
Shift register 2 (SIO2)
Receive data buffer register (SIRB2)
Receive data buffer status register (SRBS2)
Operation mode register 3 (CSIM3)
Shift register 3 (SIO3)
Display mode register (LCDM)
Display control register (LCDC)
Control register (SGCR)
Amplitude register (SGAM)
Buzzer control register (SGBR)
Compare registers (MCMP10, MCMP11, MCMP20,
MCMP21, MCMP30, MCMP31, MCMP40, MCMP41)
Timer mode control register (MCNTC)
Port mode control register (PMC)
Compare control registers (MCMPC1 to MCMPC3)
Request flag registers (IF0L, IF0H, IF1L)
Mask flag registers (MK0L, MK0H, MK1L)
Priority specify flag registers (PR0L, PR0H, PR1L)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Preliminary User's Manual U14581EJ3V0UM00
Status after Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
00H
00H
Undefined
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H