Table of Contents
Advertisement
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3
Figure 8-4. Timer Clock Select Register 3 (TCL3) Format
Address: FF75H
After Reset: 00H
Symbol
7
TCL3
0
TCL32
0
0
0
0
1
1
1
1
Cautions 1. When rewriting TCL3 to other data, stop the timer operation beforehand.
2. Bits 3 to 7 must be set to 0.
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses apply to operation with f
(2) 8-bit timer mode control registers 2, 3 (TMC2, TMC3)
TMC2 and TMC3 are registers which sets up the following five types.
<1> 8-bit counters 2 and 3 (TM2 and TM3) count operation control
<2> 8-bit counters 2 and 3 (TM2 and TM3) operation mode selection
<3> Timer output F/F (flip flop) status setting
<4> Active level selection in timer F/F control or PWM (free-running) mode
<5> Timer output control
TMC2 and TMC3 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
R/W
6
5
4
0
0
0
TCL31
TCL30
0
0
TIO3 falling edge
0
1
TIO3 rising edge
4
1
0
f
/2
(523 kHz)
X
6
1
1
f
/2
(130 kHz)
X
7
0
0
f
/2
(65.4 kHz)
X
8
0
1
f
/2
(32.7 kHz)
X
10
1
0
f
/2
X
12
1
1
f
/2
X
Preliminary User's Manual U14581EJ3V0UM00
3
2
0
TCL32
Count Clock Selection
(8.18 kHz)
(2.04 kHz)
= 8.38 MHz
X
1
0
TCL31
TCL30
125
Advertisement
Table of Contents
