(3) Priority specify flag registers (PR0L, PR0H, PR1L)
The priority specify flag registers are used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 19-4. Priority Specify Flag Register (PR0L, PR0H, PR1L) Format
Address: FFE8H After Reset: FFH R/W
Symbol
7
PR0L
PPR1
Address: FFE9H After Reset: FFH R/W
Symbol
7
PR0H
TMPR3
Address: FFEAH After Reset: FFH R/W
Symbol
7
PR1L
1
XXPRX
0
1
Cautions 1. When the watchdog timer is used in the watchdog timer mode 1, set 1 in the WDTPR flag.
2. Bits 3 to 7 of PR1L must be set to 1.
248
CHAPTER 19 INTERRUPT FUNCTIONS
6
5
PPR0
TMPR02
TMPR01
6
5
TMPR2
TMPR1
STPR
6
5
1
1
High priority level
Low priority level
Preliminary User's Manual U14581EJ3V0UM00
4
3
2
TMPR00
OVFPR
4
3
2
SRPR
SERPR
4
3
2
1
1
WTPR
Priority Level Selection
1
0
ADPR
WDTPR
1
0
CSIPR3
PPR2
1
0
WTIPR
CSIPR2