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NEC mPD1615 Preliminary User's Manual

8-bit single-chip microcontroller

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Preliminary User's Manual

µPD1615, µPD16F15,

µPD1616

8-bit Single-Chip Microcontroller

Hardware

Document No. U13635EE1V0UM00

Date Published March 1999

© NEC Corporation 1999

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Summary of Contents for NEC mPD1615

Page 1 Preliminary User’s Manual µPD1615, µPD16F15, µPD1616 8-bit Single-Chip Microcontroller Hardware Document No. U13635EE1V0UM00 Date Published March 1999 © NEC Corporation 1999...
Page 2 Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.
Page 3: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 4 µPD1615, µPD16F15, µPD1616 Introduction Readers This manual has been prepared for user engineers who want to understand the functions of the µPD1615 subseries and design and develop its application systems and programs. µPD1615 Subseries: µPD1615, µPD16F15, µPD1616. Purpose This manual is intended for users to understand the functions described in the Organization below. Organization The µPD1615 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 series).
Page 5 µPD1615, µPD16F15, µPD1616 Chapter Organization This manual devides the descriptions for the subseries into different chapters as shown below. Read only the chapters related to the device you use. µPD1615 µPD16F15 µPD1616 Chapter ¡ ¡ ¡ Chapter 1 Outline ¡ ¡...
Page 6 µPD1615, µPD16F15, µPD1616 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for µPD1615 subseries Document No. Document name Japanese English µPD1615 Preliminary Product Information —...
Page 7 IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Electric Static Discharge (ESD) Test MEM-539 — Semiconductor Devices Quality Assurance Guide MEI-603...
Page 8: Table Of Contents
µPD1615, µPD16F15, µPD1616 Table of Contents Chapter 1 Outline ......................26 1.1 Features ..............................26 1.2 Application ............................26 1.3 Ordering Information ........................... 26 1.4 Pin Configuration (Top View) ......................27 1.5 78K/0 Series Development ........................30 1.6 Block Diagram ............................. 31 1.7 Overview of Functions .........................
Page 9 µPD1615, µPD16F15, µPD1616 Chapter 3 CPU Architecture ..................51 3.1 Memory Space ............................51 3.1.1 Internal program memory space ..................... 53 3.1.2 Internal data memory space ......................55 3.1.3 Special function register (SFR) area ....................55 3.1.4 Data memory addressing ......................... 56 3.2 Processor Registers ..........................
Page 10 µPD1615, µPD16F15, µPD1616 Chapter 5 Clock Generator .................... 95 5.1 Clock Generator Functions ......................... 95 5.2 Clock Generator Configuration ......................96 5.3 Clock Generator Control Register ...................... 97 5.4 System Clock Oscillator ........................98 5.4.1 Main system clock oscillator ......................98 5.4.2 Subsystem clock oscillator ......................
Page 11 µPD1615, µPD16F15, µPD1616 Chapter 8 Watch Timer ....................167 8.1 Watch Timer Functions ........................167 8.2 Watch Timer Configuration ........................ 168 8.3 Watch Timer Mode Register (WTM) ....................169 8.4 Watch Timer Operations ........................170 8.4.1 Watch timer operation ........................170 8.4.2 Interval timer operation ........................
Page 12 µPD1615, µPD16F15, µPD1616 Chapter 13 Serial Interface Channel 30 ..............203 13.1 Serial Interface Channel 30 Functions ..................203 13.2 Serial Interface Channel 30 Configuration ..................204 13.3 List of SFRs (Special Function Registers) ..................204 13.4 Serial Interface Control Registers ....................205 13.5 Serial Interface Operations ......................
Page 13 µPD1615, µPD16F15, µPD1616 15.4 VAN UART Registers ........................243 15.4.1 Rank0 Transmission Register (RK0_REG) .................. 244 15.4.2 In Frame Response Register (IFR_REG) ..................245 15.4.3 Control Register (CTRL_REG) ..................... 247 15.4.4 Configuration Register (CONF_REG) ..................250 15.4.5 Diagnosis Control Register (DIAG_CTRL_REG) ................ 253 15.4.6 Mask1 registers (MSK1_MSB_REG, MSK1_LSB_REG) ..............
Page 14 µPD1615, µPD16F15, µPD1616 Chapter 18 Interrupt Functions ................... 307 18.1 Interrupt Function Types ........................307 18.2 Interrupt Sources and Configuration ..................... 308 18.3 Interrupt Function Control Registers ..................... 311 18.4 Interrupt Servicing Operations ....................... 317 18.4.1 Non-maskable interrupt request acknowledge operation ............317 18.4.2 Maskable interrupt request acknowledge operation ..............
Page 15 µPD1615, µPD16F15, µPD1616 Chapter 22 Instruction Set ..................349 22.1 Legends Used in Operation List ..................... 350 22.1.1 Operand identifiers and description methods ................350 22.1.2 Description of “operation” column ..................... 351 22.1.3 Description of “flag operation” column ..................351 22.2 Operation List ...........................
Page 16 µPD1615, µPD16F15, µPD1616 Contents of Figures Figure No. Title Page Pin Configuration µPD1615, µPD16F15 ............... Pin Configuration µPD1616 ..................Block Diagram µPD1615, µPD16F15 ................Block Diagram µPD1616 ....................Connection of IC Pins ....................Pin Input/Output Circuits .................... Memory Map (µPD1615, µPD1616) ................Memory Map (µPD16F15) ....................
Page 17 µPD1615, µPD16F15, µPD1616 Figure No. Title Page Block Diagram of Clock Generator ................Processor Clock Control Register Format ..............External Circuit of Main System Clock Oscillator ............ External Circuit of Subsystem Clock Oscillator ............Examples of Oscillator with Bad Connection (3/3) ........... 100 Main System Clock Stop Function (2/2) ..............
Page 18 µPD1615, µPD16F15, µPD1616 Figure No. Title Page 6-28 Timing of One-Shot Pulse Output Operation with Software Trigger ....... 136 6-29 Control Register Settings for One-Shot Pulse Output with External Trigger ..137 6-30 Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified) ........................
Page 19 µPD1615, µPD16F15, µPD1616 Figure No. Title Page 10-1 Remote Controlled Output Application Example ............180 10-2 Clock Output Control Circuit Block Diagram ............181 10-3 Clock Output Selection Register Format ..............182 10-4 Port Mode Register 12 Format ..................183 10-5 Port Function Register 12 (PF12) Format ..............
Page 20 µPD1615, µPD16F15, µPD1616 Figure No. Title Page 15-1 VAN UART Interface ....................231 15-2 VAN UART Block Diagram ................... 232 15-3 Generation of the VAN Clock ..................233 15-4 Overview of the VAN UART Registers ..............235 15-5 Prescaler in Rank 0 transmission ................236 15-6 Rank0 Transmission Register Format ................
Page 21 µPD1615, µPD16F15, µPD1616 Figure No. Title Page 16-1 LCD Controller/Driver Block Diagram ............... 270 16-2 LCD Clock Select Circuit Block Diagram ..............271 16-3 LCD Display Mode Register Format ................273 16-4 LCD Display Clock Control Register Format ............. 274 16-5 Relationship between LCD Display Data Memory Contents and Segment/Common Outputs .................
Page 22 µPD1615, µPD16F15, µPD1616 Figure No. Title Page 18-1 Basic Configuration of Interrupt Function (2/2) ............309 18-2 Interrupt Request Flag Register Format ..............312 18-3 Interrupt Mask Flag Register Format ................. 313 18-4 Priority Specify Flag Register Format ............... 314 18-5 Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register ..................
Page 23 µPD1615, µPD16F15, µPD1616 Contents of Tables Table No. Title Page 1-1 Internal high capacity ROM and RAM ....................26 1-2 Differences between Flash and Mask ROM version ................ 34 2-1-1 Pin Input/Output Types µPD1615, µPD16F15 .................. 36 2-1-2 Pin Input/Output Types µPD1616 ....................37 2-2-1 Non-Port Pins µPD1615, µPD16F15 ....................
Page 24 µPD1615, µPD16F15, µPD1616 Table No. Title Page 8-1 Interval Timer Interval Time ....................... 168 8-2 Watch Timer Configuration ....................... 168 8-3 Interval Timer Operation ........................170 9-1 Watchdog Timer Inadvertent Program Overrun Detection Times ..........173 9-2 Interval Times ............................. 173 9-3 Watchdog Timer Configuration ......................
Page 25 µPD1615, µPD16F15, µPD1616 Table No. Title Page 15-17 LA_RESP, LA ..........................260 15-18 EOM ..............................260 15-19 The bits SA and SB ........................263 15-20 The bit SC ............................263 15-21 Interrupt enable register (INT_ENABLE_REG) (2/2) ..............264 15-22 VAN clock selection register (UDLCCL) ..................266 16-1 Maximum Number of Display Pixels ....................
Page 26: Chapter 1 Outline
µPD1615, µPD16F15, µPD1616 Chapter 1 Outline (µPD1615 Subseries) 1.1 Features • Internal high capacity ROM and RAM Table 1-1: Internal high capacity ROM and RAM Item Program Data Memory Part Memory Internal High- LCD Display Internal Package Number (ROM) Speed RAM Expansion RAM µPD1615 32 K bytes...
Page 27: Pin Configuration (Top View)
µPD1615, µPD16F15, µPD1616 1.4 Pin Configuration (Top View) 80-pin plastic QFP (14 x 14 mm) µPD1615GC(A) - xxx - 8BT µPD1616GC(A) - xxx - 8BT µPD16F15GC - 8BT Figure 1-1: Pin Configuration µPD1615, µPD16F15 P105/S18 P12/ANI2 P104/S19 P11/ANI1 P10/ANI0 P103/S20 P102/S21 P101/S22 RESET...
Page 28: Pin Configuration Μpd1616
µPD1615, µPD16F15, µPD1616 Figure 1-2: Pin Configuration µPD1616 P105 P12/ANI2 P104 P11/ANI1 P10/ANI0 P103 P102 P101 RESET P100 P00/INTP0 P01/INTP1 P02/INTP2 P06/TI50/TO50 P07/TI51/TO51 Rx1VAN Rx2VAN Rx0VAN Cautions: 1. Connect IC1 (internally connected) pin directly to V 2. Connect IC2 (internally connected) pin directly to V 3.
Page 29 µPD1615, µPD16F15, µPD1616 Pin Identifications P00 to P02, P06, P07 : Port0 RxD0 : Receive Data P10 to P13 : Port1 TxD0 : Transmit Data P40 to P47 : Port4 : Sound Generator Output P80 to P87 : Port8 SGOA : Sound Generator Amplitude P90 to P97 : Port9...
Page 30: Series Development
µPD1615, µPD16F15, µPD1616 1.5 78K/0 Series Development These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 31: Block Diagram
µPD1615, µPD16F15, µPD1616 Block Diagram Figure 1-3: Block Diagram µPD1615, µPD16F15 P00-P02, Port 0 16-bitCounter TI00/TO0/P121 P06, P07 (TM0) P122/TI01 Port 1 P10-P13 8-bit Timer TI50/TO50/P06 (TM50) Port 4 P40-P47 8-bit Timer TI51/TO51/P07 (TM51) Port 8 P80-P87 SGO/SGOF/P47 Sound Generator SGOA/P46 Port 9 P90-P97...
Page 32: Block Diagram Μpd1616
µPD1615, µPD16F15, µPD1616 Figure 1-4: Block Diagram µPD1616 P00-P02, Port 0 16-bitCounter TI00/TO0/P121 P06, P07 (TM0) P122/TI01 Port 1 P10-P13 8-bit Timer TI50/TO50/P06 (TM50) Port 4 P40-P47 8-bit Timer TI51/TO51/P07 (TM51) Port 8 P80-P87 SGO/SGOF/P47 Sound Generator SGOA/P46 Port 9 P90-P97 Watchdog Timer Port 10...
Page 33: Overview Of Functions
µPD1615, µPD16F15, µPD1616 1.7 Overview of Functions Part Number µPD1615 µPD1616 µPD16F15 Item 32 Kbytes 60 Kbytes Internal high-speed RAM 1024 bytes Internal memory — LCD Display RAM 40 bytes 40 bytes Internal Expansion RAM 512 bytes 1024 bytes Memory space 64 Kbytes General registers 8 bits x 32 registers ( 8 bits x 8 registers x 4 banks)
Page 34: Mask Options
µPD1615, µPD16F15, µPD1616 1.8 Mask Options There are no mask options provided. 1.9 Differences between Flash and Mask ROM version The differences between the two versions are shown in the table below. Differences of the electrical specification are given in the data sheet. Table 1-2: Differences between Flash and Mask ROM version Flash Version Mask ROM Version...
Page 35 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 36: Chapter 2 Pin Function
µPD1615, µPD16F15, µPD1616 Chapter 2 Pin Function (µPD1615 Subseries) 2.1 Pin Function List Normal Operating Mode Pins / Pin Input/Output Types Table 2-1-1: Pin Input/Output Types µPD1615, µPD16F15 Input / Alternate After Function Output Name Function Reset INTP0 Input INTP1 Input Port 0 Input /...
Page 37: Pin Input/Output Types Μpd1616
µPD1615, µPD16F15, µPD1616 Table 2-1-2: Pin Input/Output Types µPD1616 Input / Alternate After Function Output Name Function Reset INTP0 Input INTP1 Input Port 0 Input / 5 bit input / output port INTP2 Input Output Input / output mode can be specified bit-wise TI50/TO50 Input TI51/TO51...
Page 38: Non-Port Pins
µPD1615, µPD16F15, µPD1616 2.2 Non-Port Pins Table 2-2-1: Non-Port Pins µPD1615, µPD16F15 After Alternate Pin Name Function Reset Function Pin INTP0 External interrupts with specifiable valid edges INTP1 Input (rising edge, falling edge, both rising and falling Input edges) INTP2 Input Serial interface serial data input Input...
Page 39: Non-Port Pins Μpd1616
µPD1615, µPD16F15, µPD1616 Table 2-2-2: Non-Port Pins µPD1616 After Alternate Pin Name Function Reset Function Pin INTP0 External interrupts with specifiable valid edges INTP1 Input (rising edge, falling edge, both rising and falling Input edges) INTP2 Input Serial interface serial data input Input P127 Output...
Page 40: Description Of Pin Functions
µPD1615, µPD16F15, µPD1616 2.3 Description of Pin Functions 2.3.1 P00 to P02, P06 and P07 (Port 0) This is a 5-bit input/output port. Beside serving as input/output port, it supports functions as an external interrupt input, an external count clock input to the timer and a timer signal output. The following operating modes can be specified bit-wise.
Page 41: P80 To P87 (Port 8)
µPD1615, µPD16F15, µPD1616 (2) Control mode This port functions as timer input, clock output, and sound generator output. (a) SGO, SGOA and SGOF Pins for separate or composed signal ouput of the sound generator. 2.3.4 P80 to P87 (Port 8) This is an 8-bit input/output port.
Page 42: P120 To P127 (Port 12)
µPD1615, µPD16F15, µPD1616 (2) Control mode Port 11 supports the segment signal output pins (S15 to S8) of the LCD controller/driver. 2.3.8 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/from the serial interface, serial interface clock input/output, as segment signal output pins of LCD controller/driver and as processor clock output.
Page 43: Avdd/Avref
µPD1615, µPD16F15, µPD1616 2.3.11 AV A/D converter reference voltage input pin and the power supply for the A/D-converter. When A/D converter is not used, connect this pin to V 2.3.12 AV This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D converter is not used.
Page 44: Pin I/O Circuits And Recommended Connection Of Unused Pins
µPD1615, µPD16F15, µPD1616 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. For the input/output circuit configuration of each type, see table. Table 2-3-1: Types of Pin Input/Output Circuits µPD1615, µPD16F15 (1/2) Input/Output Pin Name...
Page 45 µPD1615, µPD16F15, µPD1616 Table 2-3-1: Types of Pin Input/Output Circuits µPD1615, µPD16F15 (2/2) Input/Output Pin Name Recommended Connection for Unused Pins Circuit Type P100/S23 P101/S22 P102/S21 P103/S20 Connect to V or V via a resistor individually P104/S19 P105/S18 P106/S17 P107/S16 P110/S15 P111/S14 P112/S13...
Page 46: Types Of Pin Input/Output Circuits Μpd1616 (2/2)
µPD1615, µPD16F15, µPD1616 Table 2-3-2: Types of Pin Input/Output Circuits µPD1616 (1/2) Input/Output Pin Name Recommended Connection for Unused Pins Circuit Type P00/INTP0 P01/INTP1 P02/INTP2 Connect to V or V via a resistor individually P06/TI50/TO50 P07/TI51/TO51 P10/ANI0 P11/ANI1 Connect to V or V via a resistor individually P12/ANI2...
Page 47 µPD1615, µPD16F15, µPD1616 Table 2-3-2: Types of Pin Input/Output Circuits µPD1616 (2/2) Input/Output Pin Name Recommended Connection for Unused Pins Circuit Type P100 P101 P102 P103 Connect to V or V via a resistor individually P104 P105 P106 P107 P110 P111 P112 P113...
Page 48: Pin Input/Output Circuits
µPD1615, µPD16F15, µPD1616 Figure 2-2: Pin Input/Output Circuits (1/2) Type 1 Type 2 Input data Input data Type 5 Type 8 Data P-ch Data P-ch IN/OUT IN/OUT Output N-ch disable Output N-ch disable Input enable Type 9 P-ch Comparator N-ch (Threshold Voltage) Input enable...
Page 49 µPD1615, µPD16F15, µPD1616 Figure 2-2: Pin Input/Output Circuits (2/2) Type 17-C Type 17 Data Data P-ch P-ch IN/OUT IN/OUT Output Output N-ch N-ch disable disable Input enable P-ch P-ch N-ch N-ch P-ch P-ch Data Data N-ch N-ch P-ch P-ch N-ch N-ch Type 18 Type 19...
Page 50 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 51: Chapter 3 Cpu Architecture
µPD1615, µPD16F15, µPD1616 Chapter 3 CPU Architecture 3.1 Memory Space The memory map of the µPD1615, µPD1616 is shown in Figure 3-1. Figure 3-1: Memory Map (µPD1615, µPD1616) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits...
Page 52: Memory Map (Μpd16F15)
µPD1615, µPD16F15, µPD1616 The memory map of the µPD16F15 is shown in Figure 3-2. Figure 3-2: Memory Map (µPD16F15) FFFFH Special Function Registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-speed RAM 1024 x 8 bits FE20H...
Page 53: Internal Program Memory Space
µPD1615, µPD16F15, µPD1616 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The µPD1615 subseries have various size of internal ROMs or Flash EPROM as shown below. Table 3-1: Internal ROM Capacities Part Number Internal ROM...
Page 54: Vectored Interrupts
µPD1615, µPD16F15, µPD1616 (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
Page 55: Internal Data Memory Space
µPD1615, µPD16F15, µPD1616 3.1.2 Internal data memory space The µPD1615 subseries units incorporate the following RAMs. (1) Internal high-speed RAM This is a 1024 x 8-bit configuration in the area FB00H to FEFFH 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory.
Page 56: Data Memory Addressing
µPD1615, µPD16F15, µPD1616 3.1.4 Data memory addressing The µPD1615 subseries is provided with a varity of addressing modes which take account of memory manipulability, etc. Special addressing methods are possible to meet the functions of the special function registers (SFRs) and general registers. The data memory space is the entire 64K-byte space (0000H to FFFFH).
Page 57: Data Memory Addressing (Μpd16F15)
µPD1615, µPD16F15, µPD1616 Figure 3-4: Data Memory Addressing (µPD16F15) FFFFH Special Function Registers SFR Addressing (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short Direct General Registers Register Addressing Addressing 32 x 8 bits FEE0H FEDFH Internal High-speed RAM FE20H 1024 x 8 bits FB1FH...
Page 58: Processor Registers
µPD1615, µPD16F15, µPD1616 3.2 Processor Registers The µPD1615 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The control registers consist of a program counter, a program status word and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 59 µPD1615, µPD16F15, µPD1616 (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledge is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag.
Page 60: Stack Pointer Configuration
µPD1615, µPD16F15, µPD1616 (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7: Stack Pointer Configuration The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 61: General Registers
µPD1615, µPD16F15, µPD1616 3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
Page 62: Special Function Register (Sfr)
µPD1615, µPD16F15, µPD1616 3.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions.
Page 63: Special Function Register List
µPD1615, µPD16F15, µPD1616 Table 3-3: Special Function Register List (1/2) Address SFR Name Symbol Manipulatable Bit Unit After 1 bit 8 bits 16 bits Reset ¡ ¡ FF00H Port 0 — ¡ ¡ FF01H Port 1 — ¡ ¡ FF04H Port 4 —...
Page 64 µPD1615, µPD16F15, µPD1616 Table 3-3: Special Function Register List (2/2) Manipulatable Bit Unit After Address SFR Name Symbol Reset 1 bit 8 bits 16 bits ¡ ¡ FF60H 16-bit timer mode control register 0 TMC0 — ¡ FF61H Prescaler mode register 0 PRM0 —...
Page 65: Instruction Address Addressing
µPD1615, µPD16F15, µPD1616 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 66: Immediate Addressing
µPD1615, µPD16F15, µPD1616 3.3.2 Immediate addressing Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory space. CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.
Page 67 µPD1615, µPD16F15, µPD1616 3.3.3 Table indirect addressing Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
Page 68: Register Addressing
µPD1615, µPD16F15, µPD1616 3.3.4 Register addressing Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. Figure 3-14: Register Addressing...
Page 69: Operand Address Addressing
µPD1615, µPD16F15, µPD1616 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.
Page 70: Register Addressing
µPD1615, µPD16F15, µPD1616 3.4.2 Register addressing The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 71: Direct Addressing
µPD1615, µPD16F15, µPD1616 3.4.3 Direct addressing The memory indicated by immediate data in an instruction word is directly addressed. Operand format Table 3-6: Direct Addressing Identifier Description addr16 Label or 16-bit immediate data Description example MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 72: Short Direct Addressing
µPD1615, µPD16F15, µPD1616 3.4.4 Short direct addressing The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space, from FE20H to FF1FH. An internal high-speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 73: Special Function Register (Sfr) Addressing
µPD1615, µPD16F15, µPD1616 3.4.5 Special function register (SFR) addressing The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 74: Register Indirect Addressing
µPD1615, µPD16F15, µPD1616 3.4.6 Register indirect addressing The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code.
Page 75: Based Addressing
µPD1615, µPD16F15, µPD1616 3.4.7 Based addressing 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1).
Page 76: Based Indexed Addressing
µPD1615, µPD16F15, µPD1616 3.4.8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).
Page 77 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 78: Chapter 4 Port Functions
µPD1615, µPD16F15, µPD1616 Chapter 4 Port Functions 4.1 Port Functions The µPD1615 subseries units incorporate four input ports and fifty-three input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 79: Pin Input/Output Types Μpd1615, Μpd16F15
µPD1615, µPD16F15, µPD1616 Table 4-1: Pin Input/Output Types µPD1615, µPD16F15 Input / Alternate After Function Output Name Function Reset INTP0 Input INTP1 Input Port 0 Input / 5 bit input / output port INTP2 Input Output Input / output mode can be specified bit-wise TI50/TO50 Input TI51/TO51...
Page 80: Pin Input/Output Types Μpd1616
µPD1615, µPD16F15, µPD1616 Table 4-2: Pin Input/Output Types µPD1616 Input / Alternate After Function Output Name Function Reset INTP0 Input INTP1 Input Port 0 Input / 5 bit input / output port INTP2 Input Output Input / output mode can be specified bit-wise TI50/TO50 Input TI51/TO51...
Page 81: Port Configuration
µPD1615, µPD16F15, µPD1616 4.2 Port Configuration A port consists of the following hardware: Table 4-3: Port Configuration Item Configuration Port mode register (PMm: m = 0, 4, 8 to 12) Control register Port function register (PFm: m = 8 to 12) Port Total: 57 ports 4.2.1 Port 0...
Page 82: P00 To P02 And P06, P07 Configurations
µPD1615, µPD16F15, µPD1616 Figure 4-2: P00 to P02 and P06, P07 Configurations Selector PORT P00/INTP0, P01/INTP1, Output Latch P02/INTP02, (P00 to P02, P06/TI50/TO50, P06, P07) P07/TI51/TO51 PM00 to PM02, P06, P07 PM : Port mode register : Port 0 read signal WR : Port 0 write signal...
Page 83: Port 1
µPD1615, µPD16F15, µPD1616 4.2.2 Port 1 Port 1 is a 4-bit input only port. Dual-functions include an A/D converter analog input. Figure 4-3 shows a block diagram of port 1. Figure 4-3 P10 to P13 Configurations P10/ANI0 P13/ANI13 : Port 1 read signal...
Page 84: Port 4
µPD1615, µPD16F15, µPD1616 4.2.3 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 1-bit units. Dual-function includes the sound generator output. RESET input sets port 4 to input mode. Figure 4- 4 shows a block diagram of port 4.
Page 85: Port 8
µPD1615, µPD16F15, µPD1616 4.2.4 Port 8 Port 8 is an 8-bit input/output port with output latch. P80 to P87 pins can be specified as input mode/ output mode in 1-bit units with the port mode register 8 (PM8). Dual-function includes the segment signal outputs of LCD controller driver. The dual-function can be selected with the port function register 8 (PF8).
Page 86: Port 9
µPD1615, µPD16F15, µPD1616 4.2.5 Port 9 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 9. Dual-function includes the segment signal outputs of LCD controller driver. The dual-function can be specified with the port function register 9 (PF9).
Page 87: Port 10
µPD1615, µPD16F15, µPD1616 4.2.6 Port 10 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 10. These pins are dual function pins and serve as segment signal output of LCD controller driver. The dual-function can be specified with the port function register 10 (PF10).
Page 88: Port 11
µPD1615, µPD16F15, µPD1616 4.2.7 Port 11 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 11. These pins are dual function pins and serve as segment signal output of LCD controller driver. The dual-function can be specified with the port function register 11 (PF11).
Page 89: P120 To P127 Configurations
µPD1615, µPD16F15, µPD1616 4.2.8 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with a port mode register 12. These pins are dual function pins and serve as segment signal output of LCD controller driver. The dual-function can be specified with the port function register 12 (PF12).
Page 90: Port Function Control Registers
µPD1615, µPD16F15, µPD1616 4.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0, PM4, PM8 to PM12) • Port function registers (PFm : m = 8 to 12) (1) Port mode registers (PM0, PM4, PM8 to PM12) These registers are used to set port input/output in 1-bit units.
Page 91: Port Mode Register Format
µPD1615, µPD16F15, µPD1616 Figure 4-10: Port Mode Register Format Symbol Address After Reset R/W FF20H PM07 PM06 PM02 PM01 PM00 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 FF28H PM97 PM96 PM95 PM94 PM93...
Page 92: Port Function Register (Pf8 To Pf12) Format
µPD1615, µPD16F15, µPD1616 3) Port function register (PF8 to PF12) This register is used to set LCD segment function of ports 8 to 12. PF8 to PF12 are set with an 1-bit or 8-bit manipulation instruction. RESET input set this registors to 00H. Figure 4-11: Port Function Register (PF8 to PF12) Format PF87 PF86...
Page 93: Port Function Operations
µPD1615, µPD16F15, µPD1616 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 94 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 95: Chapter 5 Clock Generator
µPD1615, µPD16F15, µPD1616 Chapter 5 Clock Generator 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 3.9 to 8.1 MHz.
Page 96: Clock Generator Configuration
µPD1615, µPD16F15, µPD1616 5.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 5-1: Clock Generator Configuration Item Configuration Control register Processor clock control register (PCC) Main system clock oscillator Oscillator Subsystem clock oscillator Figure 5-1: Block Diagram of Clock Generator Subsystem Watch Timer Clock...
Page 97: Clock Generator Control Register
µPD1615, µPD16F15, µPD1616 5.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). (1) Processor clock control register (PCC) The PCC selects a CPU clock and the division ratio, determines whether to make the main system clock oscillator operate or stop.
Page 98: System Clock Oscillator
µPD1615, µPD16F15, µPD1616 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, the clock signal to the X1 pin and an inversed phase clock signal to the X2 pin.
Page 99: Subsystem Clock Oscillator
µPD1615, µPD16F15, µPD1616 5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a RC-resonator (standard: 40kHz) connected to the CL1 and CL2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the CL1 pin and open the CL2 pin.
Page 100 µPD1615, µPD16F15, µPD1616 Figure 5-5: Examples of Oscillator with Bad Connection (1/3) (a) Wiring of connection (b) A signal line crosses over circuits is too long oscillation circuit lines PORTn (n = 0, 4, 8 to 12) Figure 5-5: Examples of Oscillator with Bad Connection (2/3) (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor...
Page 101: When No Subsystem Clocks Are Used
µPD1615, µPD16F15, µPD1616 Figure 5-5: Examples of Oscillator with Bad Connection (3/3) Signals are fetched (f) Signal conductors of the main and sub- system clock are parallel and near each other CL1 and CL2 are wiring in parallel Caution: In Figure 6-5 (f), CL1 and X1 are wired in parallel. Thus, the cross-talk noise of X1 may increase with CL1, resulting in malfunctioning.
Page 102: Clock Generator Operations
µPD1615, µPD16F15, µPD1616 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f • Subsystem clock f • CPU clock f •...
Page 103: Main System Clock Operations
µPD1615, µPD16F15, µPD1616 5.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 104: Subsystem Clock Operations
µPD1615, µPD16F15, µPD1616 Figure 5-6: Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 5.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
Page 105: Changing System Clock And Cpu Clock Settings
µPD1615, µPD16F15, µPD1616 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 106: System Clock And Cpu Clock Switching Procedure
µPD1615, µPD16F15, µPD1616 5.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 5-7: System Clock and CPU Clock Switching RESET Interrupt Request Signal SystemClock CPUClock Minimum Maximum Speed Subsystem Clock High-Speed Speed Operation...
Page 107 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 108: Chapter 6 16-Bit Timer/ Event Counter
µPD1615, µPD16F15, µPD1616 Chapter 6 16-Bit Timer/ Event Counter 6.1 16-bit Timer/Event Counter Function 16-bit timer/event counter (TM0) has the following functions: • Interval timer • PPG output • Pulse width measurement • External event counter • Square wave output •...
Page 109: 16-Bit Timer/Event Counter Configuration
µPD1615, µPD16F15, µPD1616 6.2 16-bit Timer/Event Counter Configuration 16-bit timer/event counter (TM0) consists of the following hardware: Table 6-1: Configuration of 16-bit Timer/Event Counter (TM0) Item Configuration Timer register 16 bits x 1 (TM0) Register Capture/compare register: 16 bits x 2 (CR00, CR01) Timer output 1 (TO0) 16-bit timer mode control register (TMC0)
Page 110 µPD1615, µPD16F15, µPD1616 1) 16-bit timer register (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 111: Valid Edge Of Ti00 Pin And Valid Edge Of Capture Trigger Of Capture/Compare Register
µPD1615, µPD16F15, µPD1616 2) Capture/compare register 00 (CR00) CR00 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRC00) of the capture/compare control register 0.
Page 112 µPD1615, µPD16F15, µPD1616 (3) Capture/compare register 01 (CR01) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 of the capture/compare control register 0 (CRC0).
Page 113: 16-Bit Timer/Event Counter Control Register
µPD1615, µPD16F15, µPD1616 16-Bit Timer/Event Counter Control Register The following four types of registers control 16-bit timer/event counter (TM0). • 16-bit timer mode control register (TMC0) • Capture/compare control register (CRC0) • 16-bit timer output control register (TOC0) • Prescaler mode register 0 (PRM0) •...
Page 114 µPD1615, µPD16F15, µPD1616 Figure 6-2: Format of 16-Bit Timer Mode Control Register (TMC0) Address: FF60H After Reset: 00H Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Operating Mode Selection of TO0 Generation of TMC03 TMC02 TMC01 Clear mode and output timing interrupt clear mode Operation stop Not affected...
Page 115 µPD1615, µPD16F15, µPD1616 Cautions 1. Before changing the clear mode and TO0 output timing, be sure to stop the timer operation (reset TMC02 and TMC03 to 0, 0). 2. The valid edge of the TI00 pin is selected by using the prescaler mode register 0 (PRM0).
Page 116 µPD1615, µPD16F15, µPD1616 (2) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00 and CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 to 00H. Figure 6-3: Format of Capture/Compare Control Register 0 (CRC0) Address: FF62H After Reset: 00H Symbol...
Page 117 µPD1615, µPD16F15, µPD1616 (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter (TM0) output control circuit by setting or resetting the R-S flip-flop, enabling or disabling reverse output, enabling or disabling output of 16-bit timer/counter (TM0), enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software.
Page 118 µPD1615, µPD16F15, µPD1616 (4) Prescaler mode register 0 (PRM0) This register selects a count clock of the 16-bit timer/event counter (TM0) and the valid edge of TI00, TI01 input. PRM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PRM0 to 00H.
Page 119 µPD1615, µPD16F15, µPD1616 (5) Port mode register 12 (PM12) This register sets port 12 input/output in 1-bit units. When using the P121/TO0/TI00/S6 pin for timer output, set PM121 and the output latch of P121 to 0. PM12 is set with an 1-bit or 8-bit memory manipulation instruction. RESET input sets PM12 value to FFH.
Page 120: 16-Bit Timer/Event Counter Operations
µPD1615, µPD16F15, µPD1616 6.4 16-Bit Timer/Event Counter Operations 6.4.1 Operation as interval timer (16 bits) The 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) are set as shown in Figure 6-8. In this case, 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
Page 121 µPD1615, µPD16F15, µPD1616 Figure 6-9: Configuration of Interval Timer 16-bit capture/compare register 00 (CR00) INTTM00 fx/2 fx/2 fx/2 OVF0 16-bit timer register (TM0) TI01 Clear circuit Figure 6-10: Timing of Interval Timer Operation Count clock TM0 count value 0000H 0001H 0000H 0001H 0000H 0001H Count starts...
Page 122: Ppg Output Operation
µPD1615, µPD16F15, µPD1616 6.4.2 PPG output operation The 16-bit timer/counter can be used for PPG (Programmable Pulse Generator) output by setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-11. The PPG output function outputs a rectangular wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count value set in advance to the 16-bit capture/compare register 01 (CR01).
Page 123: Pulse Width Measurement
µPD1615, µPD16F15, µPD1616 6.4.3 Pulse width measurement The 16-bit timer register (TM0) can be used to measure the pulse widths of the signals input to the TI00 and TI01 pins. Measurement can be carried out with TM0 used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TI00 pin.
Page 124 µPD1615, µPD16F15, µPD1616 Figure 6-13: Configuration for Pulse Width Measurement with Free Running Counter fx/2 fx/2 OVF0 16-bit timer register (TM0) fx/2 16-bit capture/compare register 01 TI00 (CR01) INTTM00 Internal bus Figure 6-14: Timing of Pulse Width Measurement with Free Running Counter and One Capture Register (with both edges specified) Count clock TM0 count value...
Page 125 µPD1615, µPD16F15, µPD1616 (2) Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TI00 and TI01 pins can be measured when the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 6-14). When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0) is input to the TI00 pin, the value of the TM0 is loaded to the 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
Page 126 µPD1615, µPD16F15, µPD1616 • Capture operation (free running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 6-16: CR01 Capture Operation with Rising Edge Specified Count clock TI00 Rising edge detection CR01 INTTM01 Figure 6-17: Timing of Pulse Width Measurement with Free Running Counter (with both edges...
Page 127 µPD1615, µPD16F15, µPD1616 (3) Pulse width measurement with free running counter and two capture registers When the 16-bit timer register (TM0) is used as a free running counter (refer to Figure 6-17), the pulse width of the signal input to the TI00 pin can be measured. When the edge specified by bits 4 and 5 (ES00 and ES01) of the prescaler mode register 0 (PRM0) is input to the TI00 pin, the value of TM0 is loaded to the 16-bit capture/compare register 01 (CR01), and an external interrupt request signal (INTTM01) is set.
Page 128 µPD1615, µPD16F15, µPD1616 Figure 6-19: Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers (with rising edge specified) Count clock TM0 count value 0000H 0001H FFFFH 0000H TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 OVF0...
Page 129 µPD1615, µPD16F15, µPD1616 (4) Pulse width measurement by restarting When the valid edge of the TI00 pin is detected, the pulse width of the signal input to the TI00n pin can be measured by clearing the 16-bit timer register (TM0) once and then resuming counting after loading the count value of TM0 to the 16-bit capture/compare register 01 (CR01).
Page 130: Operation As External Event Counter
µPD1615, µPD16F15, µPD1616 Figure 6-21: Timing of Pulse Width Measurement by Restarting (with rising edge specified) Count clock TM0 count value 0000H 0001H 0000H 0001H 0000H 0001H TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 D1 x 1 D2 x 1 6.4.4 Operation as external event counter 16-bit timer/event counter can be used as an external event counter which counts the number of clock...
Page 131 µPD1615, µPD16F15, µPD1616 Figure 6-22: Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 132: Operation To Output Square Wave
µPD1615, µPD16F15, µPD1616 Figure 6-24: Timing of External Event Counter Operation (with rising edge specified) TI00 pin input TM0 count value 0000H 0001H 0003H 0004H 0005H N - 1 0000H 0002H 0002H 0001H 0003H CR00 INTTM00 Caution: Read TM0 when reading the count value of the external event counter. 6.4.5 Operation to output square wave The 16-bit timer/event counter can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00).
Page 133 µPD1615, µPD16F15, µPD1616 Figure 6-25: Set Contents of Control Registers in Square Wave Output Mode (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 134: Operation To Output One-Shot Pulse
µPD1615, µPD16F15, µPD1616 6.4.6 Operation to output one-shot pulse 16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and an external trigger (TI00/TO0 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0 pin by setting the 16-bit timer mode control register (TMC0) and by setting bit 6 (OSPT) of TOC0 by software.
Page 135 µPD1615, µPD16F15, µPD1616 Figure 6-27: Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 136 µPD1615, µPD16F15, µPD1616 Figure 6-28: Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMC0 (TM0 count starts) Count clock TM0 count value 0000H 0001H N + 1 0000H N - 1 M - 1 0000H 0001H 0002H CR01 set value CR00 set value OSPT...
Page 137 µPD1615, µPD16F15, µPD1616 Figure 6-29: Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts at valid edge of TI00/TO0 pin (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 138 µPD1615, µPD16F15, µPD1616 Figure 6-30: Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified) Sets 08H to TMC0 (TM0 count starts) Count clock TM0 count value 0000 0001 0000 M+2 M+3 CR01 set value CR00 set value TI00 pin input INTTM01 INTTM00...
Page 139: 16-Bit Timer/Event Counter Operating Precautions
µPD1615, µPD16F15, µPD1616 6.5 16-Bit Timer/Event Counter Operating Precautions (1) Error on starting timer An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started. This is because the 16-bit timer register (TM0) is started asynchronously in respect to the count pulse. Figure 6-31: Start Timing of 16-Bit Timer Register Count pulses 0000H...
Page 140 µPD1615, µPD16F15, µPD1616 (4) Data hold timing of capture register If the valid edge is input to the TI00 pin while the 16-bit capture/compare register 01 (CR01) is read, CR01 performs the capture operation, but this capture value is not guaranteed. However, the interrupt request flag (INTTM01) is set as a result of detection of the valid edge.
Page 141 µPD1615, µPD16F15, µPD1616 7) Operation of OVF0 flag The OVF0 flag is set to 1 in the following case: Select mode in which 16-bit timer/counter is cleared and started on coincidence between TM0 and CR00. ↓ Set CR00 to FFFFH ↓...
Page 142 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 143: Chapter 7 8-Bit Timer/Event Counters 50 And 51
µPD1615, µPD16F15, µPD1616 Chapter 7 8-Bit Timer/Event Counters 50 and 51 7.1 8-Bit Timer/Event Counters 50 and 51 Functions The 8-bit timer event counters 50 and 51 (TM50, TM51) have the following functions. • Interval timer • External event counter •...
Page 144: 8-Bit Timer/Event Counter 50 Interval Times
µPD1615, µPD16F15, µPD1616 (1) 8-bit interval timer Interrupts are generated at the preset time intervals. Table 7-1: 8-Bit Timer/Event Counter 50 Interval Times Minimum Interval Width Maximum Interval Width Resolution x 1/f (250 ns) x 1/f (64 µs) x 1/f (250 ns) x 1/f (1 µs)
Page 145: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges
µPD1615, µPD16F15, µPD1616 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-3: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution...
Page 146: 8-Bit Timer/Event Counters 50 And 51 Configurations
µPD1615, µPD16F15, µPD1616 7.2 8-Bit Timer/Event Counters 50 and 51 Configurations The 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-5: 8-Bit Timer/Event Counters 50 and 51 Configurations Item Configuration Timer register 8 bits x 2 (TM50, TM51) Register Compare register 8 bits x 2 (CR50, CR51) Timer output...
Page 147 µPD1615, µPD16F15, µPD1616 Figure 7-2: 8-Bit Timer/Event Counter 51 Block Diagram Internal Bus 8-Bit Compare Register (CR51) Match INTTM51 fx/2 Note fx/2 fx/2 Output 8-Bit Timer fx/2 Control TO51/P07/TI51 Register n (TM51) fx/2 TI51/P07/TO51 Clear Selector Timer Clock Select 8-Bit Timer Mode Register 51 Control Register 51 Internal Bus...
Page 148 µPD1615, µPD16F15, µPD1616 Figure 7-3: Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit TMCn1 TMCn6 RESET LVRn LVSn TO50/P06/TI50, TO51/P07/TI51 TMCn1 PM06, TMCn6 P06, P07 PM07 Output Latch INTTMn PWM Output Circuit Timer Output F/F2 TCEn INTTMn Level OVFn...
Page 149: 8-Bit Timer/Event Counters 50 And 51 Control Registers
µPD1615, µPD16F15, µPD1616 7.3 8-Bit Timer/Event Counters 50 and 51 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 50 and 51. • Timer clock select register 50 and 51 (TCL50, TCL51) • 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) •...
Page 150 µPD1615, µPD16F15, µPD1616 (2) Timer clock select register 51 (TCL51) This register sets count clocks of 8-bit timer register 51. TCL51 is set with an 8-bit memory manipulation instruction. RESET input sets TCL51 to 00H. Figure 7-5: Timer Clock Select Register 51 Format Address After Reset Symbol...
Page 151 µPD1615, µPD16F15, µPD1616 (3) 8-bit timer mode control register 50 (TMC50) This register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/ disabling.
Page 152 µPD1615, µPD16F15, µPD1616 (4) 8-bit timer mode control register 51 (TMC51) This register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. It selects the R-S flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 51 timer output enabling/ disabling.
Page 153 µPD1615, µPD16F15, µPD1616 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P06/TI50/TO50 and P07/TI51/TO51 pins for timer output, set PM06, PM07 and output latches of P06 and P07 to 0. PM0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 154: 8-Bit Timer/Event Counters 50 And 51 Operations
µPD1615, µPD16F15, µPD1616 7.4 8-Bit Timer/Event Counters 50 and 51 Operations 7.4.1 Interval timer operations Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 7-9 allows operation as an interval timer. Interrupts are generated repeatedly using the count value preset in 8- bit compare registers (CR50 and CR51) as the interval.
Page 155 µPD1615, µPD16F15, µPD1616 Figure 7-10: Interval Timer Operation Timings (2/3) (b) When CRn = 00H Count clock TCEn INTTMn TIOn Interval time (c) When CRn = FFH Count clock TCEn INTTMn Interrupt received Interrupt received TIOn Interval time Remark: n = 50, 51...
Page 156 µPD1615, µPD16F15, µPD1616 Figure 7-10: Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N) Count clock TCEn INTTMn TIOn CRn transition TMn overflows since M < N (e) Operated by CR5n transition (M > N) Count clock NÐ1 MÐ...
Page 157: 8-Bit Timer/Event Counters 50 Interval Times
µPD1615, µPD16F15, µPD1616 Table 7-6: 8-Bit Timer/Event Counters 50 Interval Times TCLn2 TCLn1 TCLn0 Minimum Interval Time Maximum Interval Time Resolution Tin input cycle x Tin input cycle Tin input edge input cycle Tin input cycle x Tin input cycle Tin input edge input cycle x 1/f (250 ns)
Page 158: External Event Counter Operation
µPD1615, µPD16F15, µPD1616 7.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI50/P06/ TO50 and TI51/P07/TO51 pins with 8-bit timer registers 50 and 51 (TM50 and TM51). TM50 and TM51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (TCL50 and TCL51) is input.
Page 159: Square-Wave Output
µPD1615, µPD16F15, µPD1616 7.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR51). The TO50/P06/TI50 or TO51/P07/TI51 pin output status is reversed at intervals of the count value preset to CR50 or CR51 by setting bit 1 (TMC501) and bit 0 (TOE50) of the 8-bit timer output control register 5 (TMC50), or bit 1 (TMC511) and bit 0 (TOE51) of the 8-bit timer mode control register 6 (TMC51) to 1.
Page 160: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges
µPD1615, µPD16F15, µPD1616 Table 7-8: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution x 1/f (250 ns) x 1/f (64 µs) x 1/f (250 ns) x 1/f (1 µs) x 1/f (256 µs) x 1/f (1 µs) x 1/f (4 µs)
Page 161: Pwm Output Operations
µPD1615, µPD16F15, µPD1616 7.4.4 PWM output operations Setting the 8-bit timer mode control registers (TMC50 and TMC51) as shown in Figure 7-15 allows operation as PWM output. Pulses with the duty rate determined by the values preset in 8-bit compare registers (CR50 and CR51) output from the TO50/P06/TI50 or TO51/P07/TI51 pin.
Page 162 µPD1615, µPD16F15, µPD1616 Figure 7-16: PWM Output Operation Timing (Active high setting) CRn Changing Count Clock N+3 00 TMn Count Value TCEn INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Remark: n = 50, 51 Figure 7-17: PWM Output Operation Timings (CRn0 = 00H, active high setting) CRn Changing Count Clock TMn Count Value...
Page 163 µPD1615, µPD16F15, µPD1616 Figure 7-18: PWM Output Operation Timings (CRn = FFH, active high setting) Count Clock TMn Count Value TCEn INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark: n = 50, 51 Figure 7-19: PWM Output Operation Timings (CRn changing, active high setting) CRn Changing Count Clock...
Page 164: Cautions On 8-Bit Timer/Event Counters 50 And 51
µPD1615, µPD16F15, µPD1616 7.5 Cautions on 8-Bit Timer/Event Counters 50 and 51 (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. This is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse.
Page 165 µPD1615, µPD16F15, µPD1616 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR51) are changed are smaller than those of 8-bit timer registers (TM50 and TM51), TM50 and TM51 continue counting, overflow and then restarts counting from 0.
Page 166 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 167: Chapter 8 Watch Timer
µPD1615, µPD16F15, µPD1616 Chapter 8 Watch Timer 8.1 Watch Timer Functions The watch timer has the following functions: • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. The figure 8-1 shows Watch Timer Block Diagram. Figure 8-1: Block Diagram of Watch Timer Clear 5-bit counter...
Page 168: Watch Timer Configuration
µPD1615, µPD16F15, µPD1616 (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 0.5 second intervals. (2) Interval timer Interrupt requests (INTWTI) are generated at the preset time interval. Table 8-1: Interval Time Selection Interval When operated at When operated at...
Page 169: Watch Timer Mode Register (Wtm)
µPD1615, µPD16F15, µPD1616 8.3 Watch Timer Mode Register (WTM) This register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. WTM is set with a 1-bit or 8-bit memory manipulation instruction.
Page 170: Watch Timer Operations
µPD1615, µPD16F15, µPD1616 8.4 Watch Timer Operations 8.4.1 Watch timer operation When the 32.768-kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second interval. The watch timer is generated interrupt request at the constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register is set to 1, the 5-bit counter is cleared and the count operation stops.
Page 171 µPD1615, µPD16F15, µPD1616 Figure 8-3: Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWT Interrupt time of watch timer (0.5s) Interrupt time of watch timer (0.5s) Interval timer interrupt INTWTI Interval timer Remark: : Watch timer clock frequency...
Page 172 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 173: Chapter 9 Watchdog Timer
µPD1615, µPD16F15, µPD1616 Chapter 9 Watchdog Timer 9.1 Watchdog Timer Functions The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution: Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). (1) Watchdog timer mode An inadvertent program loop is detected.
Page 174: Watchdog Timer Configuration
µPD1615, µPD16F15, µPD1616 9.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 9-3: Watchdog Timer Configuration Item Configuration Timer clock select register (WDCS) Control register Watchdog timer mode register (WDTM) Figure 9-1: Watchdog Timer Block Diagram Internal Bus Prescaler TMMK...
Page 175: Watchdog Timer Control Registers
µPD1615, µPD16F15, µPD1616 9.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock.
Page 176 µPD1615, µPD16F15, µPD1616 (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3: Watchdog Timer Mode Register Format Symbol Address AfterReset...
Page 177: Watchdog Timer Operations
µPD1615, µPD16F15, µPD1616 9.4 Watchdog Timer Operations 9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (WDCS0 to WDCS2) of the timer clock select register (WDCS).
Page 178: Interval Timer Operation
µPD1615, µPD16F15, µPD1616 9.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (WDTM3) of the watchdog timer mode register (WDTM) is set to 0, respectively.
Page 179 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 180: Chapter 10 Clock Output Control Circuit
µPD1615, µPD16F15, µPD1616 Chapter 10 Clock Output Control Circuit 10.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the clock output selection register (CKS) are output from the PCL/P120/S7 pin.
Page 181: Clock Output Control Circuit Configuration
µPD1615, µPD16F15, µPD1616 10.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 10-1: Clock Output Control Circuit Configuration Item Configuration Clock output selection register (CKS) Control register Port mode register 3 (PM3) Figure 10-2: Clock Output Control Circuit Block Diagram Synchronizing Circuit...
Page 182: Clock Output Function Control Registers
µPD1615, µPD16F15, µPD1616 10.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Clock output selection register (CKS) • Port mode register 12 (PM12) (1) Clock Output Selection Register (CKS) This register sets PCL output clock.
Page 183 µPD1615, µPD16F15, µPD1616 2) Port Mode Register 12 (PM12) This register sets port 12 input/output in 1-bit units. When using the P120/PCL/S7 pin for clock output function, set PM120 and output latch of P120 to 0. PM12 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM12 to FFH.
Page 184 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 185: Chapter 11 A/D Converter
µPD1615, µPD16F15, µPD1616 Chapter 11 A/D Converter 11.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 4 analog input channels (ANI0 to ANI3). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution One channel of analog input is selected from ANI0 to ANI3, and A/D conversion is repeatedly executed with a resolution of 8 bits.
Page 186: A/D Converter Configuration
µPD1615, µPD16F15, µPD1616 Figure 11-2: Power-Fail Detection Function Block Diagram PFCM PFEN ANI0/P10 INTAD ANI1/P11 A/D converter Comparator ANI2/P12 ANI3/P13 Power-fail compare threshold value PFEN PFCM register (PFT) Power-fail compare mode register (PFM) Internal bus 11.2 A/D Converter Configuration A/D converter consists of the following hardware. Table 11-1: A/D Converter Configuration Item Configuration...
Page 187 µPD1615, µPD16F15, µPD1616 (3) Sample & hold circuit The sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion.
Page 188: A/D Converter Control Registers
µPD1615, µPD16F15, µPD1616 11.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter. • A/D converter mode register (ADM1) • Analog input channel specification register (ADS1) • Power-fail compare mode register (PFM) • Power-fail compare threshold value register (PFT) (1) A/D converter mode register (ADM1) This register sets the conversion time for analog input to be A/D converted, conversion start/stop and external trigger.
Page 189 µPD1615, µPD16F15, µPD1616 (2) Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 11-4: Analog Input Channel Specification Register (ADS1) Format Symbol Address After Reset R/W...
Page 190 µPD1615, µPD16F15, µPD1616 (3) Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. RESET input clears PFM to 00H. Figure 11-5: Power-Fail Compare Mode Register (PFM) Format Symbol Address After Reset R/W PFEN PFCM FF82H PFEN Enables Power-Fail Comparison...
Page 191: A/D Converter Operations
µPD1615, µPD16F15, µPD1616 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 192 µPD1615, µPD16F15, µPD1616 Figure 11-7: Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR1 result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software.
Page 193: Input Voltage And Conversion Results
µPD1615, µPD16F15, µPD1616 11.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the following expression.
Page 194: A/D Converter Operation Mode
µPD1615, µPD16F15, µPD1616 11.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI3 with the analog input channel specification register (ADS1) and A/D conversion is performed.
Page 195 µPD1615, µPD16F15, µPD1616 Figure 11-9: A/D Conversion ADM1 rewrite ADCS1 = 1 ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Stop Conversion results are not stored ADCR1 ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied...
Page 196: A/D Converter Precautions
µPD1615, µPD16F15, µPD1616 11.5 A/D Converter Precautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop conversion.
Page 197 µPD1615, µPD16F15, µPD1616 (4) Noise countermeasures To maintain 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI3. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in the Figure 11-11 to reduce noise.
Page 198 µPD1615, µPD16F15, µPD1616 (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required if a change of analog input pin is performed during A/D conversion. The A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite, if the ADIF is read immediately after the ADS1 rewrite, the ADIF may be set despite to the fact that the A/D conversion for the post-change analog...
Page 199: Cautions On Emulation
µPD1615, µPD16F15, µPD1616 11.6 Cautions on Emulation To perform debugging with an in-circuit emulator (IE-78001-R-A), the D/A converter mode register (DAM0) must be set. DAM0 is a register used to set the I/O board (IE-78K0-NS-P04). 11.6.1 D/A converter mode register (DAM0) DAM0 is necessary if the power-fail detection function is used.
Page 200 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 201: Chapter 12 Serial Interface Outline
µPD1615, µPD16F15, µPD1616 Chapter 12 Serial Interface Outline 12.1 Serial Interface Outline The µPD1615 subseries incorporates two channels of serial interfaces. Table 12-1: Differences between the Serial Interface Channels Serial Transfer Mode µPD1615 µPD16F15 µPD1616 ¡ ¡ ¡ SIO 30 (3-wire serial I/O) ¡...
Page 202 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 203: Chapter 13 Serial Interface Channel 30
µPD1615, µPD16F15, µPD1616 Chapter 13 Serial Interface SIO30 13.1 Serial Interface Channel 30 Functions The SIO30 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used if serial transfer is not performed. For details, see 15.5.1 Operation Stop Mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 204: Serial Interface Channel 30 Configuration
µPD1615, µPD16F15, µPD1616 13.2 Serial Interface Channel 30 Configuration The SIO30 includes the following hardware. Table 13-1: Composition of SIO30 Item Configuration Registers Serial I/O shift register 30 (SIO30) Control registers Serial operation mode register 30 (CSIM30) (1) Serial I/O shift register 30 (SIO30) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.
Page 205: Serial Interface Control Registers
µPD1615, µPD16F15, µPD1616 13.4 Serial Interface Control Registers The SIO3 uses the following type of register for control functions. • Serial operation mode register 30 (CSIM30) (1) Serial operation mode register 30 (CSIM30) This register is used to enable or disable SIO30’s serial clock, operation modes, and specific operations.
Page 206: Serial Interface Operations
µPD1615, µPD16F15, µPD1616 13.5 Serial Interface Operations This section explains on two modes of SIO30. 13.5.1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power consumption. During the operation stop mode, the pins can be used as normal I/O ports as well. (1) Register settings The operation stop mode can be set via the serial operation mode register 30 (CSIM30).
Page 207: Three-Wire Serial I/O Mode
µPD1615, µPD16F15, µPD1616 13.5.2 Three-wire serial I/O mode The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock- synchronous serial interface, a display controller, etc. This mode executes the data transfer via three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 208 µPD1615, µPD16F15, µPD1616 (2) Communication Operations In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received synchronized with the serial clock. The serial I/O shift register 30 (SIO30) is shifted synchronized with the falling edge of the serial clock. The transmission data is held in the SO3 latch and is output from the SO3 pin.
Page 209 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 210: Chapter 14 Serial Interface Uart
µPD1615, µPD16F15, µPD1616 Chapter 14 Serial Interface UART 14.1 Serial Interface UART Functions The serial interface UART has the following two modes. (1) Operation stop mode This mode is used if the serial transfer is performed to reduce power consumption. For details, see 14.5.1 Operation Stop Mode.
Page 211: Serial Interface Uart Configuration
µPD1615, µPD16F15, µPD1616 14.2 Serial Interface UART Configuration The UART includes the following hardware. Table 14-1: Configuration of UART Item Configuration Registers Transmit shift register 1 (TXS0) Receive shift register 1 (RXS0) Receive buffer register (RXB0) Control registers Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0) (1) Transmit shift register 1 (TXS0)
Page 212: List Of Sfrs (Special Function Registers)
µPD1615, µPD16F15, µPD1616 14.3 List of SFRS (Special Function Registers) Table 14-2: List of SFRs (Special Function Registers) Units available for bit Value SFR name Symbol manipulation when reset 1 bit 8 bits 16 bits Transmit shift register TXS0 ¢ —...
Page 213 µPD1615, µPD16F15, µPD1616 Figure 14-2: Format of Asynchronous Serial Interface Mode Register (ASIM0) Address: FFA0H When reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 TXE0 RXE0 Operation mode RxD0/P123/S4pin function TxD0/P124/S3pin function Operation stop Port function Port function UART0 mode Serial operation Port function (receive only)
Page 214 µPD1615, µPD16F15, µPD1616 (2) Asynchronous serial interface status register (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-3: Format of Asynchronous Serial Interface Status Register (ASIS0) Address: FFA1H When reset: 00H Symbol...
Page 215 µPD1615, µPD16F15, µPD1616 Figure 14-4: Format of Baud Rate Generator Control Register (BRGC0) Address: FFA2H When reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.00 MHz) TPS02 TPS01 TPS00 Source clock selection for 5-bit counter MDL03 MDL02 MDL01 MDL00...
Page 216: Serial Interface Operations
µPD1615, µPD16F15, µPD1616 14.5 Serial Interface Operations This section explains the three modes of the UART. 14.5.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, pins can be used as ordinary ports. (1) Register settings Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM0).
Page 217 µPD1615, µPD16F15, µPD1616 (a) Asynchronous serial interface mode register (ASIM0) ASIM0 can be set by 1-bit or 8-bit memory manipulation instructions. When RESET is input, its value is 00H. Figure 14-6: Asynchronous serial interface mode register (ASIM0) Address: FFA0H When reset: 00H Symbol ASIM0 TXE0...
Page 218 µPD1615, µPD16F15, µPD1616 (b) Asynchronous serial interface status register (ASIS0) ASIS0 can be read using an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-7: Asynchronous serial interface status register (ASIS0) Address: FFA1H When reset: 00H Symbol ASIS0 OVE0...
Page 219 µPD1615, µPD16F15, µPD1616 (c) Baud rate generator control register (BRGC0) BRGC0 can be set by an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-8: Baud rate generator control register (BRGC0) Address: FFA2H When reset: 00H Symbol BRGC0 TPS02...
Page 220 µPD1615, µPD16F15, µPD1616 The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Use of main system clock to generate a transmit/receive clock for baud rate The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula.
Page 221 µPD1615, µPD16F15, µPD1616 • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 14-4 describes the relation between the main system clock and the baud rate and Figure 14-9 shows an example of a baud rate error tolerance range.
Page 222 µPD1615, µPD16F15, µPD1616 Figure 14-9: Error Tolerance (when k = 0), including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception 30.45T...
Page 223 µPD1615, µPD16F15, µPD1616 (2) Communication operations (a) Data format As shown in Figure 14-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIM0) is used to set the character bit length, parity selection, and stop bit length within each data frame.
Page 224 µPD1615, µPD16F15, µPD1616 (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 225 µPD1615, µPD16F15, µPD1616 (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt (INTST) is issued.
Page 226 µPD1615, µPD16F15, µPD1616 (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface mode register (ASIM0), and input data via RxD pin is sampled. The serial clock specified by ASIM0 is used when sampling the RxD0 pin. When the RxD0 pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output if half of the specified baud rate time has elapsed.
Page 227 µPD1615, µPD16F15, µPD1616 (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (ASIS0), a receive error interrupt (INTSER) will occur.
Page 228: Standby Function
µPD1615, µPD16F15, µPD1616 14.6 Standby Function Serial transfer operations can be performed during HALT mode. During STOP mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (ASIM0), transmit shift register (TXS0), receive shift register (RxS0), and receive buffer register (RXB0) remain as they were just before the clock was stopped.
Page 229 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 230: Chapter 15 Van Controller
µPD1615, µPD16F15, µPD1616 Chapter 15 VAN Controller 15.1 Features - The VAN UART is compatible with the ISO 11519 VAN standard, Part 3, revision 4.00. - The VAN UART executes all the VAN frame types: * Programmed in autonomous mode (RANK bit = 0), it performs the transmission and reception of data frames (transmits from the SOF field or from the IDEN field) and read frames as well as the in frame response.
Page 231: Overview Of The Van Bus
µPD1615, µPD16F15, µPD1616 15.2 Overview of the VAN Bus 15.2.1 VAN UART Description The VAN UART cell integrated in this microcontroller is comform to the VAN Standard (ISO 11519, Part 3, Rev 4.00). 15.2.2 VAN UART Interface Figure 15-1: VAN UART Interface UDL-I/F Data Bus bridge Block...
Page 232 µPD1615, µPD16F15, µPD1616 Figure 15-2: VAN UART Block Diagram Rx0VAN TxVAN Rx1VAN Rx2VAN Diagnosis Logic VAN CORE VAN UART Registers TX/RX Shift Register RKO_REG CRC Generator/Checker IFR_REG CTRL_REG Bit Time Logic CONF_REG DIAG_CTRL_REG Error Bit Stream Management Processor Logic Interface Management Logic Internal Bus Interface Management Logic (IML) : The IML executes the CPU’s transmission and reception commands and controls the data transfer...
Page 233 µPD1615, µPD16F15, µPD1616 This divider divides the input clock by the value defined in the VAN Prescaler. The following picture shows the generation of the VAN clock : Figure 15-3: Generation of the VAN Clock CPU's 1, 2, 3, 5 —...
Page 234 µPD1615, µPD16F15, µPD1616 Cyclic Redundancy Check (CRC) generator and checker : The CRC generator consists of a 15-bit shift register and the logic required to generate the checksum of the bit-stream. It informs the EML about the result of a receiver checksum. The checksum is generated by the polynomial : g(x) = x This logic performs the calculation of the CRC in transmission and in reception.
Page 235: Functional Description
µPD1615, µPD16F15, µPD1616 15.3 Functional description 15.3.1 Overview of the VAN UART Registers Figure 15-4: Overview of the VAN UART Registers RK0_REG F800H IFR_REG F801H IFR7 IFR6 IFR5 IFR4 IFR3 IFR2 IFR1 IFR0 STOP- ACK- LAST- SOFT- CTRK_REG F802H BYTE RESET CONFIG_REG F803H...
Page 236: Autonomous Mode Functions
µPD1615, µPD16F15, µPD1616 15.3.2 Autonomous mode functions 15.3.2.1 Autonomous mode features The user sets the VAN UART in autonomous mode by setting the RANK bit to 0. The transmission clock is the quartz clock divided by the prescaler chosen by the user in the DIAG_CTRL_REG register.
Page 237: Transmission Features In Autonomous Mode
µPD1615, µPD16F15, µPD1616 Table 15-1: Network Speeds as a Function of the Quartz Clock and the Chosen Division Ratio Quartz (MHz) Ratio Network speed (KTS) 0000 62.5 0001 31.25 62.5 0010 62.5 0011 62.5 0100 31.25 62.5 0101 15.625 31.25 62.5 0110 31.25...
Page 238: Synchronous Mode Functions
µPD1615, µPD16F15, µPD1616 15.3.3 Synchronous mode functions 15.3.3.1 Synchronous mode features The user sets the VAN UART in synchronous mode by setting the RANK bit to 1 in the control register CTRL_REG. The transmission clock is the quartz clock divided by the prescaler chosen by the user in the DIAG_CTRL_REG register.
Page 239: Reception Of The Crc
µPD1615, µPD16F15, µPD1616 15.3.5.2 Reception of the CRC For high-speed applications, the UART incorporates a CRC module, which compares the received CRC with the calculated CRC. This comparison is carried out in transmission and in reception, giving place, in the latter case, to the transmission of a possible acknowledge. 15.3.6 Control of the acknowledge bit In reception, if the EOD symbol has been detected and if the CRC is correct, then if the ACK-REQ bit is set to 1 in the CTRL_REG register before the end of the EOD field, a positive acknowledge...
Page 240: Interrupt Control
µPD1615, µPD16F15, µPD1616 15.3.7.2 Interrupt control An error is signalled by an interrupt if the user defines it. Any interrupt that would have been generated after the detection of an error is deleted. The interrupt sources are listed below: LA_RESP Lost arbitration in the RTR bit (Response) End of message Lost arbitration...
Page 241 µPD1615, µPD16F15, µPD1616 It signifies that a byte must be loaded into the RK0_REG or IFR_REG register, but can be ignored if the microcontroller has no more bytes to transmit. In this case, it sets the LAST-BYTE bit in the control register CTRL_REG for the transmission of the CRC.
Page 242 µPD1615, µPD16F15, µPD1616 It can be disabled in the INT_ENABLE_REG register by the FTE bit. - FR interrupt The FR interrupt appears after a code violation, a CRC error or a format error (acknowledgement error in reception) or a reception lock-up (when there is no read access to the reception register between the reception of two consecutive bytes).
Page 243: Van Uart Registers
µPD1615, µPD16F15, µPD1616 15.4 VAN UART Registers The VAN UART consists of the following registers. Table 15-4: VAN UART Registers Manipulatable bit unit Address Register NAME SYMBOL After Reset 1bit 8bit 16bit F800H Rank 0 Register RK0_REG F801H In Frame Transmit Register IFR_REG F802H Control Register...
Page 244: Rank0 Transmission Register (Rk0_Reg)
µPD1615, µPD16F15, µPD1616 15.4.1 Rank0 Transmission Register (RK0_REG) The rank0 transmission register is loaded by the microcontroller to trigger a transmit request. RK0_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input set this register to FFH. Figure 15-6: Rank0 Transmission Register Format Symbol Address...
Page 245: In Frame Response Register (Ifr_Reg)
µPD1615, µPD16F15, µPD1616 15.4.2 In Frame Response Register (IFR_REG) The IFR Transmit Register is written when the user wish to transmit an In Frame Response (IFR). IFR_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input set this register to FFH. Figure 15-7: Frame Responce Register Format Symbol...
Page 246 µPD1615, µPD16F15, µPD1616 Figure 15-8: Frame Responce Register Function RTR=0 DAT=33 VAN UART Other In Frame Lost Responce Arbitration First Byte Received INT0 INT1 INT2 WRITE RK0 and IFR Registers with first Data Byte...
Page 247: Control Register (Ctrl_Reg)
µPD1615, µPD16F15, µPD1616 15.4.3 Control Register (CTRL_REG) The Control Register is used to control the VAN UART during the transmisision or to initiate a RESET. CTRL_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input set this register to 00H. Figure 15-9: Control Register Format After...
Page 248 µPD1615, µPD16F15, µPD1616 Figure 15-10: Control Register Block Diagram Byte 2 of the Frame memorised IDEN3 IDEN2 IDEN1 IDEN0 EXT in the microcontroller CTRL_REG SOFT STOP LAST of the UART RESET BYTE Therefore, a mask with 04h of the 2nd byte needs to be made and written in the control register. Figure 15-11: Control Register Function CRC2...
Page 249 µPD1615, µPD16F15, µPD1616 The UART places the 2 CRC bytes after it. This may occur during a write frame or a read frame: in the case of a write frame, the last byte of data is signalled after the last data is transmitted. In the case of a read frame, the last byte is signalled after loading the 2nd identifier.
Page 250: Configuration Register (Conf_Reg)
µPD1615, µPD16F15, µPD1616 15.4.4 Configuration Register (CONF_REG) The Configuration Register is used to configure the interrupt generation, the UART mode and response and the mask function. CONF_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input set this register to 08H. Figure 15-13: Configuration Register (CONF_REG) Format Symbol...
Page 251 µPD1615, µPD16F15, µPD1616 Case where IT12 = 1 Figure 15-15: Case where IT12 = 1 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 IDEN2 + COM IDEN1 Reception INT2 INT1 "Byte"...
Page 252 µPD1615, µPD16F15, µPD1616 MSK1, MSK0: Mask Enable / Disable Table 15-12: Mask Enable / Disable MSK1 MSK0 Function Masks 1 and 2 activated (all identifiers filtered) Mask1 inhibited Mask2 inhibited Masks 1 and 2 inhibited (all identifiers accepted) MSK1 and MSK0 combinations allow enabling or disabling all or part of the mask mechanism applied on the identification field described further on.
Page 253: Diagnosis Control Register (Diag_Ctrl_Reg)
µPD1615, µPD16F15, µPD1616 15.4.5 Diagnosis Control Register (DIAG_CTRL_REG) The Diagnosis Control Register allows to configure the bus speed, the communication mode and diagnostic functions. DIAG_CTRL_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input set this register to 17H. Figure 15-16: Diagnosis Control Register (DIAG_CTRL_REG) Format After...
Page 254 µPD1615, µPD16F15, µPD1616 Table 15-13: Prescaler - Network Speeds as a Function of the Quartz Clock and the Chosen Division Ratio Quartz (MHz) Ratio Network speed (KTS) 0000 62.5 0001 31.25 62.5 0010 62.5 0011 62.5 0100 31.25 62.5 0101 15.625 31.25 62.5...
Page 255 µPD1615, µPD16F15, µPD1616 DIA1, DIA0: Choice of communication mode Table 15-16: Choice of Communication Mode DIA1 DIA0 Communication mode Forced operation on RXD0 Forced operation on RXD1 Forced operation on RXD2 Automatic operation The 2 least significant bits DIA1 and DIA0 allow the user to choose the communication mode.
Page 256: Mask1 Registers (Msk1_Msb_Reg, Msk1_Lsb_Reg)
µPD1615, µPD16F15, µPD1616 15.4.6 Mask1 registers (MSK1_MSB_REG, MSK1_LSB_REG) These 2 registers allow to compare the 12 bits of the VAN identification field plus the EXT bit. MSK1_MSB_REG, MSK1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input sets these registers to 00H. Figure 15-18-1: Mask1 register MSK1_MSB_REG Format After...
Page 257: Acceptance Code 1 Registers (Ac1_Msb_Reg, Ac1_Lsb_Reg)
µPD1615, µPD16F15, µPD1616 15.4.7 Acceptance Code 1 registers (AC1_MSB_REG, AC1_LSB_REG) These 2 registers allow to choose the code acceptance which is the value of the identification field that the user wish to match with. They work together with the MSK1 registers. AC1_MSB_REG, AC1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction.
Page 258: Mask2 Registers (Msk2_Msb_Reg, Msk2_Lsb_Reg)
µPD1615, µPD16F15, µPD1616 15.4.8 Mask2 registers (MSK2_MSB_REG, MSK2_LSB_REG) These 2 registers allow to compare the 12 bits of the VAN identification field plus the EXT bit. MSK1_MSB_REG, MSK1_LSB_REG is set with a 1-bit or 8-bit manipulation instruction. RESET input sets these registers to 00H. Figure 15-20-1: Mask2 register MSK2_MSB_REG Format After...
Page 259: Acceptance Code 2, 3 And 4 Registers
µPD1615, µPD16F15, µPD1616 15.4.9 Acceptance Code 2, 3 and 4 Registers (AC2_MSB_REG, AC2_LSB_REG, AC3_MSB_REG, AC3_LSB_REG, AC4_MSB_REG, AC4_LSB_REG) These 6 registers allow to choose the code acceptance which is the value of the identification field that the user wish to match with. They work together with the MSK2 registers. AC2_MSB_REG, AC2_LSB_REG, AC3_MSB_REG, AC3_LSB_REG, AC4_MSB_REG, AC4_LSB_REG are set with a 1-bit or 8-bit manipulation instruction.
Page 260: Status Register (Stat_Reg)
µPD1615, µPD16F15, µPD1616 15.4.10 Status Register (STAT_REG) This register allows to control a lost arbitration, the end of message, the acknowledge and the error type during a transmission or a reception. STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction. RESET input sets this register to 08H.
Page 261 µPD1615, µPD16F15, µPD1616 The EOM flag is set when a VAN frame is transmitted or received correctly or incorrectly. These 2 kinds of EOM may be signalled either by interrupt (INT0), if enabled by the user (EOME bit of the INT_ENABLE_REG register), or by reading the EOM bit in the status register STAT_REG.
Page 262: Receive Register (Rec_Reg)
µPD1615, µPD16F15, µPD1616 15.4.11 Receive register (REC_REG) This register is used as receive register of a reception. STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction. RESET input sets this register to FFH. Figure 15-23: Receive register (REC_REG) Format After Symbol Address...
Page 263: Diagnosis Status Register (Diag_Stat_Reg)
µPD1615, µPD16F15, µPD1616 15.4.12 Diagnosis Status Register (DIAG_STAT_REG) This register is used for the diagnose of the receive lines. DIAG_STAT_REG can be read with a 1-bit or an 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 15-24: Diagnosis Status Register (DIAG_STAT_REG) Format After Symbol Address...
Page 264: Interrupt Enable Register (Int_Enable_Reg)
µPD1615, µPD16F15, µPD1616 15.4.13 Interrupt enable register (INT_ENABLE_REG) This register allows to enable/disable the interrupt sources of the VAN UART. INT_ENABLE_REG is set with a 1-bit or an 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 15-25: Interrupt enable register (INT_ENABLE_REG) Format After Symbol Address...
Page 265 µPD1615, µPD16F15, µPD1616 Table 15-21: Interrupt enable register (INT_ENABLE_REG) (2/2) This interrupt will coincide with an EOM interrupt, as an error will cause a premature end of message. FRE: FR Enable Fail receive interrupt Failed receive interrupt disabled Failed receive interrupt enabled This interrupt will coincide with an EOM interrupt, as an error will cause a premature end of message.
Page 266: Van Clock Selection Register (Udlccl)
µPD1615, µPD16F15, µPD1616 15.4.14 VAN clock selection register (UDLCCL) This SFR register enables the clock suppply to the VAN UART. UDLCCL is set with a 1-bit or an 8-bit manipulation instruction. RESET input sets this register to 00H. Figure 15-26: VAN clock selection register (UDLCCL) Format Addres After Symbol...
Page 267: Van Uart Initialisation
µPD1615, µPD16F15, µPD1616 15.5 VAN UART initialisation 1) Enable the clock via UDLCCL SFR register. 2) Configure the component: a) Choose the UART mode of operation owing to the RANK bit in the configuration register b) Enable or disable the In Frame Response using the IFR bit in the same register c) Enable or disable the generation of the IT12 interrupt using the IT12 bit in the same register d) Enable or disable the identifier filtering mechanism using the MSK1 and MSK0 bits in the same register...
Page 268 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 269: Chapter 16 Lcd Controller/Driver
µPD1615, µPD16F15, µPD1616 Chapter 16 LCD Controller/Driver 16.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the µPD1615 subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic writing of the display data memory.
Page 270: Lcd Controller/Driver Configuration
µPD1615, µPD16F15, µPD1616 16.2 LCD Controller/Driver Configuration The LCD controller/driver is composed of the following hardware. Table 16-2: LCD Controller/Driver Configuration Item Configuration Segment signals : 40 Display outputs Segment signal input/output port dual function : 40 Common signals : 4 (COM0 to COM3) LCD display mode register (LCDM) Control registers LCD display control register (LCDC)
Page 271 µPD1615, µPD16F15, µPD1616 Figure 16-2: LCD Clock Select Circuit Block Diagram Prescaler fx/2 LCDCL LCDC3 LCDC2 LCD display mode register Internal bus Remarks: 1. LCDCL : LCD clock 2. f : LCD clock frequency...
Page 272: Lcd Controller/Driver Control Registers
µPD1615, µPD16F15, µPD1616 16.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following two registers. • LCD display mode register (LCDM) • LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register sets display operation enabling/ disabling, the LCD driving power and the LCD display mode.
Page 273 µPD1615, µPD16F15, µPD1616 Table 16-3: Frame Frequencies (Hz) Frame frequency (Hz) LCDC3 LCDC2 x=4.0 MHz x=8.0 MHz Static Static 81.4 162.8 40.7 30.5 81.4 30.5 20.3 15.3 40.7 30.5 30.5 15.3 10.2 30.5 20.3 15.3 Remark: 1.Figures in parentheses apply to operation with fx = 4.0 MHz or fx = 8.0 MHz.
Page 274 µPD1615, µPD16F15, µPD1616 (2) LCD display clock control register (LCDC) This register sets the LCD clock. LCDC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC to 00H. Figure 16-4: LCD Display Clock Control Register Format Symbol Address AfterReset...
Page 275: Lcd Controller/Driver Settings
µPD1615, µPD16F15, µPD1616 16.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. When the LCD controller/driver is used, the watch timer should be set to the operational state beforehand. <1>Set the initial value in the display data memory (FA00H to FA27H). <2>Set the pins to be used as segment outputs in the port function registers (PF8 to PF12).
Page 276: Lcd Display Data Memory
µPD1615, µPD16F15, µPD1616 16.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA00H to FA27H. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 16-5 shows the relationship between the LCD display data memory contents and the segment outputs/common outputs.
Page 277: Common Signals And Segment Signals
µPD1615, µPD16F15, µPD1616 16.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage V As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven by AC voltage.
Page 278 µPD1615, µPD16F15, µPD1616 (3) Common signal and segment signal output waveforms The voltages shown in Table 16-5 are output in the common signals and segment signals. The ±V ON voltage is only produced when the common signal and segment signal are both at the selection voltage;...
Page 279 µPD1615, µPD16F15, µPD1616 Figure 16-6 shows the common signal waveform, and Figure 16-7 shows the common signal and segment signal voltages and phases. Figure 16-6: Common Signal Waveform (a) Static display mode COMn (Static) Remarks: 1.T: One LCDCL cycle 2.TF: Frame frequency (b) 1/2 bias method COMn (Divided by 2)
Page 280 µPD1615, µPD16F15, µPD1616 Figure 16-7: Common Signal and Static Signal Voltages and Phases (a) Static display mode Selected Not selected Common signal Segment signal Remark: T : One LCDCL cycle (b) 1/2 bias method Selected Not selected Common signal Segment signal Remark: T : One LCDCL cycle (c) 1/3 bias method...
Page 281: Supply Of Lcd Drive Voltages Vlc0, Vlc1, Vlc2
µPD1615, µPD16F15, µPD1616 16.7 Supply of LCD Drive Voltages V The split resistors makes it possible to produce LCD drive voltages appropriate to the various bias methods shown in Table 16-6 without using external split resistors. Table 16-6: LCD Drive Voltages (with On-Chip Split Resistor)connected externally Bias Method No bias 1/2 bias...
Page 282 µPD1615, µPD16F15, µPD1616 Figure 16-8: LCD Drive Power Supply Connection Examples (with External Split Resistor) Note (a) Static display mode (Example with V 1 = 5 V, V = 5 V) P-ch LIPS Note: LIPS should always be set to 1 (including in standby mode). (b) 1/2 bias method (c) 1/3 bias method (Example with VDD1 = 5 V, VLCD = 5 V)
Page 283 µPD1615, µPD16F15, µPD1616 Figure 16-9: Example of LCD Drive Voltage Supply from Off-Chip P-ch LIPS 3R + r Caution: The LCD split resistors have to be set externally.
Page 284: Display Modes
µPD1615, µPD16F15, µPD1616 16.8 Display Modes 16.8.1 Static display example Figure 16-11 shows the connection of a static type 5-digit LCD panel with the display pattern shown in Figure 16-10 with segment (S0 to S39) and common (COM0) signals. The display example is “123.45,”...
Page 285 µPD1615, µPD16F15, µPD1616 Figure 16-11: Static LCD Panel Connection Example COM3 COM2 Can be shorted COM1 COM0 FA27H FA1FH FA0FH FA00H...
Page 286 µPD1615, µPD16F15, µPD1616 Figure 16-12: Static LCD Drive Waveform Examples COM0 COM0-S19 –V COM0-S20 –V...
Page 287: 2-Time-Division Display Example
µPD1615, µPD16F15, µPD1616 16.8.2 2-time-division display example Figure 16-14 shows the connection of a 2-time-division type 10-digit LCD panel with the display pattern shown in Figure 16-13 with segment signals (S0 to S39) and common signals (COM0, COM1). The display example is “123456.7890,” and the display data memory contents correspond to this. An explanation is given here taking the example of the eighth digit “3”...
Page 288 µPD1615, µPD16F15, µPD1616 Figure 16-14: 2-Time-Division LCD Panel Connection Example COM3 Open COM2 Open COM1 COM0 FA27H FA1FH FA0FH FA00H Remark: In bits marked X, any data can be stored because this is a 2-time-division display.
Page 289 µPD1615, µPD16F15, µPD1616 Figure 16-15: 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) COM0 COM1 +1/2V COM0-S31 –1/2V –V +1/2V COM1-S31 –1/2V –V...
Page 290: 3-Time-Division Display Example
µPD1615, µPD16F15, µPD1616 16.8.3 3-time-division display example Figure 16-17 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown in Figure 16-16 with segment signals (S0 to S38) and common signals (COM0 to COM2). The display example is “123456.7890123,” and the display data memory contents correspond to this. An explanation is given here taking the example of the eighth digit “6.”...
Page 291 µPD1615, µPD16F15, µPD1616 Figure 16-17: 3-Time-Division LCD Panel Connection Example COM3 Open COM2 COM1 COM0 F A27H FA1FH FA0FH FA00H Remarks: 1. x’ : Irrelevant bits because they have no corresponding segment in the LCD panel 2. x : Irrelevant bits because this is a 3-time-division display...
Page 292 µPD1615, µPD16F15, µPD1616 Figure 16-18: 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) COM0 COM1 COM2 +1/2V COM0-S21 –1/2V –V +1/2V COM1-S21 –1/2V –V +1/2V COM2-S21 –1/2V –V...
Page 293 µPD1615, µPD16F15, µPD1616 Figure 16-19: 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 +1/3V COM0-S21 –1/3V –V +1/3V COM1-S21 –1/3V –V +1/3V COM2-S21 –1/3V –V...
Page 294: 4-Time-Division Display Example
µPD1615, µPD16F15, µPD1616 16.8.4 4-time-division display example Figure 16-21 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown in Figure 16-20 with segment signals (S0 to S39) and common signals (COM0 to COM3). The display example is “123456.78901234567890,” and the display data memory contents correspond to this.
Page 295 µPD1615, µPD16F15, µPD1616 Figure 16-21: 4-Time-Division LCD Panel Connection Example COM3 COM2 COM1 COM0 FA27H FA1FH FA0FH FA00H...
Page 296 µPD1615, µPD16F15, µPD1616 Figure 16-22: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 +1/3V COM0-S28 –1/3V –V +1/3V COM1-S28 –1/3V –V...
Page 297 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 298: Chapter 17 Sound Generator
µPD1615, µPD16F15, µPD1616 Chapter 17 Sound Generator 17.1 Sound Generator Function The sound generator has the function to sound the buzzer from an external speaker, and the following two signals are output. (1) Basic cycle output signal (with/without amplitude) A buzzer signal with a variable frequency in a range of 0.25 to 7.3 kHz (at fx = 8.00 MHz) can be output.
Page 299: Sound Generator Configuration
µPD1615, µPD16F15, µPD1616 Figure 17-2: Concept of Each Signal Basic cycle output SGOF (without amplitude) Amplitude output SGOA Basic cycle output SGO (with amplitude) 17.2 Sound Generator Configuration The sound generator consists of the following hardware. Table 17-1: Sound Generator Configuration Item Configuration Counter...
Page 300: Sound Generator Control Registers
µPD1615, µPD16F15, µPD1616 17.3 Sound Generator Control Registers The following three types of registers are used to control the sound generator. • Sound generator control register (SGCR) • Sound generator buzzer control register (SGBR) • Sound generator amplitude control register (SGAM) (1)Sound generator control register (SGCR) SGCR is a register which sets up the following four types.
Page 301 µPD1615, µPD16F15, µPD1616 Figure 17-3: Sound Generator Control Register (SGCR) Format Symbol Address After Reset R/W SGCR SGOB SGCL2 SGCL1 SGCL0 FF66H Sound Generator Output Selection Timer operation stopped SGOF/SGO and SGOA for low-level output Sound generator operation SGOF/SGO and SGOA for output Caution: Before setting the TCE bit, set all the other bits.
Page 302 µPD1615, µPD16F15, µPD1616 The sound generator output frequency f can be calculated by the following expression. (SGCL0 – SGCL1 – 2 x SGCL2 – 7) x {fx/(SGBR + 17)} Substitute set 0 or 1 to SGCL0 to SGCL2 in the above expression. Substitute a decimal value to SGBR. Where fx = 8 MHz, SGCL0 to SGCL2 is (1, 0, 0), and SGBR0 to SGBR3 is (1, 1, 1, 1), SGBR = 15.
Page 303 µPD1615, µPD16F15, µPD1616 Figure 17-5: Sound Generator Frequency Selection SGBR SGCL2,1 (Hz) SGCL0 4-bit comparator 7352.9 3676.5 1838.2 919.1 6944.4 3472.2 1736.1 868.1 6578.9 3289.5 1644.7 822.4 6250.0 3125.0 1562.5 781.3 5952.4 2976.2 1488.1 744.0 5681.8 2840.9 1420.5 710.2 5434.8 2717.4 1358.7 679.3...
Page 304 µPD1615, µPD16F15, µPD1616 Figure 17-6: Sound Generator Amplitude Register (SGAM) Format Symbol Address After Reset R/W SGAM SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 FF67H SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 Amplitude 0/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128 10/128...
Page 305: Sound Generator Operations
µPD1615, µPD16F15, µPD1616 17.4 Sound Generator Operations 17.4.1 To output basic cycle signal SGOF (without amplitude) Select SGOF output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to “0”. The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output.
Page 306 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 307: Chapter 18 Interrupt Functions
µPD1615, µPD16F15, µPD1616 Chapter 18 Interrupt Functions 18.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
Page 308: Interrupt Sources And Configuration
µPD1615, µPD16F15, µPD1616 18.2 Interrupt Sources and Configuration There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources. Table 18-1: Interrupt Source List Basic Vector Interrupt Priority struct Interrupt request source code type (default) address type Resetting RESET Reset input...
Page 309 µPD1615, µPD16F15, µPD1616 Figure 18-1: Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Vector Table Priority Control Interrupt Address Circuit Request Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Priority Control Address Interrupt Circuit Generator...
Page 310 µPD1615, µPD16F15, µPD1616 Figure 18-1: Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (EGN, EGP) Vector Table Priority Control Address Interrupt Edge Circuit Generator Request Detector Standby Release Signal (D) Software interrupt Internal Bus Vector Table Interrupt...
Page 311: Interrupt Function Control Registers
µPD1615, µPD16F15, µPD1616 18.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
Page 312 µPD1615, µPD16F15, µPD1616 (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 313 µPD1615, µPD16F15, µPD1616 (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
Page 314 µPD1615, µPD16F15, µPD1616 (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Page 315 µPD1615, µPD16F15, µPD1616 (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) EGP and EGN specify the valid edge to be detected on pins P00 to P02. EGP and EGN can be read or written to with a 1-bit or 8-bit memory manipulation instruction. These registers are set to 00H when the RESET signal is output.
Page 316 µPD1615, µPD16F15, µPD1616 (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped.
Page 317: Interrupt Servicing Operations
µPD1615, µPD16F15, µPD1616 18.4 Interrupt Servicing Operations 18.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
Page 318 µPD1615, µPD16F15, µPD1616 Figure 18-7: Flowchart from Non-Maskable Interrupt Generation to Acknowledge Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt control...
Page 319 µPD1615, µPD16F15, µPD1616 Figure 18-9: Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction NMI Request NMI Request Reserve Execution Reserved NMI Request Processing (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine...
Page 320: Maskable Interrupt Request Acknowledge Operation
µPD1615, µPD16F15, µPD1616 18.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 321 µPD1615, µPD16F15, µPD1616 Figure 18-10: Interrupt Request Acknowledge Processing Algorithm Start xxIF = 1? Yes (Interrupt Request Generation) xxMK = 0? Interrupt request reserve Yes (High priority) xxPR = 0? No (Low Priority) Any high- priority interrupt among simultaneously generated simultaneously xxPR = 0 interrupts? generated xxPR = 0...
Page 322: Software Interrupt Request Acknowledge Operation
µPD1615, µPD16F15, µPD1616 Figure 18-11: Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks PSW and PC Save, Interrupt CPU Processing Instruction Instruction Jump to Interrupt Servicing Servicing Program xxIF (xxPR = 1) 8 Clocks xxIF (xxPR = 0) 7 Clocks Remark: 1 clock: : CPU clock)
Page 323: Multiple Interrupt Servicing
µPD1615, µPD16F15, µPD1616 18.4.4 Multiple interrupt servicing A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1) (except non-maskable interrupt). As soon as an interrupt request is acknowledged, it enters the acknowledge disable state (IE = 0).
Page 324 µPD1615, µPD16F15, µPD1616 Figure 18-13: Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE = 0 IE = 0 IE = 0 INTyy INTzz (PR = 0) (PR = 0) INTxx (PR = 1) RETI...
Page 325 µPD1615, µPD16F15, µPD1616 Figure 18-13: Multiple Interrupt Example (2/2) Example 3. A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx INTyy Servicing Servicing IE = 0 INTyy INTxx (PR = 0) (PR = 0) RETI IE = 0 1 Instruction Execution...
Page 326: Interrupt Request Reserve
µPD1615, µPD16F15, µPD1616 18.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction). •...
Page 327 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 328: Chapter 19 Standby Function
µPD1615, µPD16F15, µPD1616 Chapter 19 Standby Function 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
Page 329: Standby Function Control Register
µPD1615, µPD16F15, µPD1616 19.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 330: Standby Function Operations
µPD1615, µPD16F15, µPD1616 19.2 Standby Function Operations 19.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 19-1: HALT Mode Operating Status HALT mode setting HALT execution during main...
Page 331 µPD1615, µPD16F15, µPD1616 (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
Page 332 µPD1615, µPD16F15, µPD1616 (c) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 19-3: HALT Mode Release by RESET Input Wait HALT : 16.3 ms) Instruction RESET Signal...
Page 333: Stop Mode
µPD1615, µPD16F15, µPD1616 19.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions: 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull- up resistor to minimize leakage current at the crystal oscillator.
Page 334 µPD1615, µPD16F15, µPD1616 (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 335 µPD1615, µPD16F15, µPD1616 (b) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 19-5: Release by STOP Mode RESET Input Wait STOP : 16.3 ms) Instruction RESET Signal Oscillation...
Page 336 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 337: Chapter 20 Reset Function
µPD1615, µPD16F15, µPD1616 Chapter 20 Reset Function 20.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 338 µPD1615, µPD16F15, µPD1616 Figure 20-2: Timing of Reset Input by RESET Input Oscillation Reset Period Normal Operation Normal Operation Stabilization (Oscillation Stop) (Reset Processing) Time Wait RESET Internal Reset Signal Delay Delay High Impedance Port Pin Figure 20-3: Timing of Reset due to Watchdog Timer Overflow Normal Operation Reset Period Oscillation...
Page 339 µPD1615, µPD16F15, µPD1616 Table 20-1: Hardware Status after Reset (1/2) Hardware Status after Reset The contents of reset vector tables Note 1 Program counter (PC) (0000H and 0001H) are set Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined) Note 2...
Page 340 µPD1615, µPD16F15, µPD1616 Table 20-1: Hardware Status after Reset (2/2) Hardware Status after Reset Operating mode register 0 (CSIM30) Shift register 0 (CSIO30) Operating mode register 1 (CSIM31) Shift register 1 (CSIO31) Asynchronous mode register (ASIM0) Serial interface Asynchronous status register (ASIS0) Baudrate generator control register (BRGC0) Transmit shift register (TXS0) Receive buffer register (RXB0)
Page 341 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 342: Chapter 21 Μpd16F15
µPD1615, µPD16F15, µPD1616 Chapter 21 µPD16F15 The µPD16F15 replaces the internal mask ROM of the µPD1615 / µPD1616 with flash memory to which a program can be written, deleted and overwritten while mounted on the substrate. Table 21-1 lists the differences among the µPD16F15 and the mask ROM versions. Table 21-1: Differences among µPD16F15 and Mask ROM Versions Item µPD16F15...
Page 343: Memory Size Switching Register (Ims)
µPD1615, µPD16F15, µPD1616 21.1 Memory Size Switching Register (IMS) This register specifies the internal memory size by using the memory size switching register (IMS), so that the same memory map as on the mask ROM version can be achieved. IMS is set with an 8-bit memory manipulation instruction. RESET input sets this register to CFH.
Page 344: Internal Extension Ram Size Switching Register
µPD1615, µPD16F15, µPD1616 21.2 Internal Extension RAM Size Switching Register The µPD16F15 allow users to define its internal expansion RAM size by using the internal expansion RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different internal extension RAM is possible.
Page 345: Flash Memory Programming
µPD1615, µPD16F15, µPD1616 21.3 Flash memory programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash writer to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to the Flash Programmer.
Page 346: Flash Memory Programming Function
µPD1615, µPD16F15, µPD1616 21.3.3 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 21-5. Table 21-5: Main Functions of Flash Memory Programming Function Description Reset...
Page 347: Flash Programming Precautions
µPD1615, µPD16F15, µPD1616 Figure 21-5: Flashpro Connection Using UART Method Flash Programmer µPD 16F15 RESET RESET RXD0 TXD0 Figure 21-6: Flashpro Connection Using Pseudo 3-wire Serial I/O Flash Programmer µPD 16F15 RESET RESET (Serial clock input) (Serial data input) (Serial data output) 10.3 V applied from the on-board programming tool.
Page 348 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 349: Chapter 22 Instruction Set
µPD1615, µPD16F15, µPD1616 Chapter 22 Instruction Set This chapter describes each instruction set of the µPD1615 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL - Instruction (U12326E).”...
Page 350: Legends Used In Operation List
µPD1615, µPD16F15, µPD1616 22.1 Legends Used in Operation List 22.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 351: Description Of "Operation" Column
µPD1615, µPD16F15, µPD1616 22.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 352: Operation List
µPD1615, µPD16F15, µPD1616 22.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte r, #byte – (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte – A ← r Note 3 A, r –...
Page 353 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word rp, #word – (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word – AX ← (saddrp) AX, saddrp (saddrp) ←...
Page 354 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte A, #byte – (saddr), CY ← (saddr) – byte saddr, #byte A, CY ← A – r Note 3 A, r –...
Page 355 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A byte A, #byte – (saddr) ← (saddr) byte saddr, #byte A ← A r Note 3 A, r – r ←...
Page 356 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word ADDW AX, #word – 16-bit AX, CY ← AX – word SUBW AX, #word – operation CMPW AX, #word –...
Page 357 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) CY, saddr.bit CY ← CY sfr.bit CY, sfr.bit – CY ← CY A.bit AND1 CY, A.bit – CY ← CY PSW.bit CY, PSW.bit –...
Page 358 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 359 µPD1615, µPD16F15, µPD1616 Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 saddr.bit, $addr16 PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 360: Instructions Listed By Addressing Type
µPD1615, µPD16F15, µPD1616 22.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 361 µPD1615, µPD16F15, µPD1616 Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] $addr16 None [HL + B] First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C DBNZ...
Page 362 µPD1615, µPD16F15, µPD1616 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW MOVW...
Page 363 µPD1615, µPD16F15, µPD1616 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP...
Page 364 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 365: Appendix A Development Tools
µPD1615, µPD16F15, µPD1616 Appendix A Development Tools The following development tools are available for the development of systems that employ the µPD1615 Subseries. Figure A-1 shows the development tool configuration. Figure A-1: Development Tool Configuration Embedded Software Language Processing Software •...
Page 366: Language Processing Software
µPD1615, µPD16F15, µPD1616 A.1 Language Processing Software This assembler converts programs written in mnemonics into an object code RA78K/0 executable with a microcomputer. Assembler Package Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler is used in combination with an optional device file (DF780949).
Page 367: Flash Memory Writing Tools
µPD1615, µPD16F15, µPD1616 A.2 Flash Memory Writing Tools Dedicated flash writer for microcontrollers with on-chip flash memory. Flashpro Flash Writer Flashpro is a product of Naitoudensei Machida Seisakusho, Co., Ltd. µ PD1615 Subseries flash memory writing adapter used connected to Flashpro. Flash memory writing adapter FA-80GC-SL These are products of Naitoudensei Machida Seisakusho, Co., Ltd.
Page 368: Software (1/2)
µPD1615, µPD16F15, µPD1616 A.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operatin of the target system on a host machine. The SM78K0 operates on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
Page 369: Software (2/2)
µPD1615, µPD16F15, µPD1616 A.3.2 Software (2/2) ID78K0 This is a control program used to debug the 78K/0 Series. Integrated Debugger The graphical user interfaces employed are Windows for personal computers and OSF/Motif for EWSs, offering the standard appearance and operability typical of these interfaces.
Page 370: Os For Ibm Pc
µPD1615, µPD16F15, µPD1616 A.4 OS for IBM PC The following OSs for IBM PCs are supported. To operate SM78K0, ID78K0, and FE9200 (see B.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. Version PC DOS Ver.
Page 371: Development Environment When Using Ie-78001-R-A
µPD1615, µPD16F15, µPD1616 A.5 Development Environment when Using IE-78001-R-A When using the IE-78001-R-A as the in-circuit emulator, the following debugging tools are required. In-circuit emulator is used to debug hardware and software when an application IE-78001-R-A systems using the 78K/0 Series is developed. It suports the integrated debugger In-Circuit Emulator ID78K0.
Page 372 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 373: Appendix B Embedded Software
µPD1615, µPD16F15, µPD1616 Appendix B Embedded Software For efficient development and maintenance of the µPD1615 Subseries, the following embedded software products are available.
Page 374: Real-Time Os (1/2)
µPD1615, µPD16F15, µPD1616 B.1 Real-Time OS (1/2) µ RX78K/0 RX78K/0 is a real-time OS conforming with the ITRON specifications. Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file. µ...
Page 375: Real-Time Os (2/2)
µPD1615, µPD16F15, µPD1616 B.1 Real-Time OS (2/2) µ MX78K0 TRON specification subset OS. Nucleus of MX78K0 is supplied. This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
Page 376: Fuzzy Inference Development Support System
µPD1615, µPD16F15, µPD1616 B.2 Fuzzy Inference Development Support System FE9000/FE9200 Program that supports input, edit, and evaluation (simulation) of fuzzy knowledge Fuzzy knowledge data creation tool data (fuzzy rule and membership function). FE9200 works on Windows. µ Part number: SxxxxFE9000 (PC-9800 Series) µ...
Page 377 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 378: Appendix C Register Index
µPD1615, µPD16F15, µPD1616 Appendix C Register Index C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register 1 (ADCR1) … 186 A/D converter mode register (ADM1) … 188 Analog input channel specification register (ADS1) … 189 Asynchronous serial interface mode register (ASIM0) …...
Page 379 µPD1615, µPD16F15, µPD1616 Memory size switching register (IMS) … 382, 406 Oscillation stabilization time selection register (OSTS) … 331 Port 0 (P0) … 81 Port 1 (P1) … 83 Port 4 (P4) … 84 Port 8 (P8) … 85 Port 9 (P9) … 86 Port 10 (P10) …...
Page 380 µPD1615, µPD16F15, µPD1616 Serial I/O shift register 30 (SIO30) … 203, 204, 208 Serial operation mode register 30 (CSIM30) … 205, 206, 207 16-bit timer mode control register (TMC0) … 113, 114, 120, 122, 123, 125, 129, 133 16-bit timer output control register (TOC0) … 113, 117, 122, 133 16-bit timer register (TM0) …...
Page 381: Register Index (In Alphabetical Order With Respect To Register Symbol)
µPD1615, µPD16F15, µPD1616 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR1 : A/D conversion result register 1 ADM1 : A/D converter mode register ADS1 : Analog input channel specification register ASIM0 : Asynchronous serial interface mode register ASIS0 : Asynchronous serial interface status register BRGC0 : Baud rate generator control register...
Page 382 µPD1615, µPD16F15, µPD1616 : Port 0 : Port 1 : Port 4 : Port 8 : Port 9 : Port 10 : Port 11 : Port 12 : Processor clock contrtol register : Port function register 8 : Port function register 9 PF10 : Port function register 10 PF11...
Page 383 µPD1615, µPD16F15, µPD1616 : Successive approximation register SGAM : Sound generator amplitude register SGBC : Sound generator buzzer control register SGCR : Sound generator control register SIO30 : Serial I/O shift register 30 TCL50 : Timer clock selection register 50 TCL51 : Timer clock selection register 51 : 16-bit timer register 0...
Page 384 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 385: Appendix D Revision History
µPD1615, µPD16F15, µPD1616 Appendix D Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. Edition No. Major items revised Revised Sections...
Page 386 µPD1615, µPD16F15, µPD1616 Appendix D Revision History Edition No. Major items revised Revised Sections...
Page 387 µPD1615, µPD16F15, µPD1616 [Memo]...
Page 388 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

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