Cisco MGX MGX 8800 Hardware Installation Manual page 560

PXM45 Specifications
Table A-4
Specification
Processor clock speed and memory
specifics
Maximum switch fabric throughput
Control access
Note
Controller access port
Note
Alarm indicators (audible and visual)
BITS clock interface
Synchronization
Note
Power
Maximum power consumption
Cisco MGX 8800/8900 Series Hardware Installation Guide
A-6
PXM45 Specifications (continued)
These ports exist on the user
interface back cards.
This port exists on the PXM-HD
back card.
These clock sources satisfy
Stratum 3 requirements
Description
Clock speed: 350 MHz internal, 100 MHz external
Flash memory: 2 MB
DRAM: 256 MB
PXM45, introduced October 2000, with MGX
•
Release 2 software and 128 MB RAM
• PXM45/B, introduced October 2001, with MGX
Release 2.1 software and 256 MB RAM
PXM45/C, introduced April 2003, with MGX
•
Release 4.0 software and 512 MB RAM.
Tertiary cache: 2 MB
Secondary cache: 256 KB
BRAM: 512 KB
Hard disk: 6 GB
45 Gbps
Control port: RJ-45 receptacle, EIA/TIA-232, DTE
•
mode, asynchronous interface, 19,200 baud, 1 start
bit, 1 stop bit, no parity bits
• Maintenance port: RJ-45 receptacle, EIA/TIA-232,
DTE mode, asynchronous interface, 19,200 baud, 1
start bit, 1 stop bit, no parity bits
LAN port: RJ-45 receptacle, 10BASE-T,
•
802.3 Ethernet
Connector: OC-3 SC
Central office-compatible alarm indicators and controls
through a DB-15 receptacle
T1 and E1 with an RJ-48 receptacle
8-kHz clock derived from the following sources:
Internal 8-kHz clock (± 4.6 ppm)
•
Recovered clock from service modules or trunk line
•
interfaces
External BITS clock port
•
–48 VDC
See Table 3-6
Releases 2 - 5.2, Part Number OL-4545-01, Rev. H0, May 2006
Appendix