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Measurement example
Figure 215 Timogram with TD-SCDMA signal analyzer
Setting limit for power vs. time tests
Procedure
1.
Press the LIMIT hot key.
2.
Press the PvsT Test Limits soft key.
3.
Select the test item(s) and set the limit(s) depending on your selected measurement mode:
To set the limit for
Slot power
Downlink pilot signal power
Uplink pilot signal power
Power between on and off
portions of the downlink slots
4.
Optional. You can enable alarm sound that goes off if the measurement falls outside of the limit.
Toggle the Beep soft key between On and Off to enable or disable the beep sound.
5.
Optional. Go to SAVE/LOAD > Save, and then select Limit to save the limit settings.
See "Using save" on page 31 for more information.
Conducting modulation measurements
TD-SCDMA receivers rely on the frequency or phase quality of the QPSK or 8PSK signal in order to
achieve the expected carrier to noise performance. A transmitter with high frequency or phase error is
often still able to support phone calls during a functional test. It displays the frequency errors
numerically and graphically, showing the binary representation of the demodulated data bits of the
received signal using Constellation, Midamble Power, Code Power, and Code Error screens.
Select
Slot Power
DwPTS Power
UpPTS Power
On/Off Ratio
Using TD-SCDMA Signal Analyzer
JD780A Series Analyzers
Set
High Limit, Low Limit
High Limit, Low Limit
High Limit, Low Limit
High Limit, Low Limit
435
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