Board Features - Lattice Semiconductor LatticeECP2M PCI Express x4 User Manual

Lattice Semiconductor

Board Features

• SERDES interface to x4 PCI Express edge fingers
• DDR2 memory device
• SERDES high-speed interface SMA test points (active with LatticeECP2M-50 and larger FPGAs only) and clock
connections
• Power connections and power sources
®
• ispVM programming support
• On-board and external reference clock sources
• Interchangeable clock oscillators
• On-board reference clock management using Lattice ispClock™ devices
– ORCAstra demonstration software interface via standard ispVM JTAG connection
– Various high-speed layout structures
• User defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user's guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 1 shows the functional partitioning of the board.
Figure 2. LatticeECP2M PCI Express x4 Evaluation Board
PCI Express (x4)
Edge Fingers
4 SMAs for External
Clock Sources
Oscillators
SMAs for a Single
1 Quad of 3G
(SRIO x1, x4),
BNC Connector
XAUI
LatticeECP2Mxx
672 fpBGA
General Purpose DDR2
I/Os - Memory
Switches/LEDs Component
3
LatticeECP2M PCI Express x4
Evaluation Board User's Guide
ispVM/JTAG
8 LVDS Paired SMAs for
Demo of LVDS I/O
Performance
FPGA Loader
SPI Flash Device