Chapter 3: Creating The Gtz Ibert Core - Xilinx Virtex-7 FPGA VC7222 Getting Started Manual

Creating the GTZ IBERT Core
This section provides a procedure to create the GTZ IBERT core with integrated
SuperClock-2 controller. Vivado® Design Suite 2015.1 is required to rebuild the design
shown here.
For more details on generating IBERT cores, see the Vivado Design Suite User Guide:
Programming and Debugging (UG908)
See steps 1–5 in
Note:
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
[Ref 3].
Chapter 2, Creating the GTH IBERT Core
www.xilinx.com
Chapter 3
to learn how to create a new IP core.
Send Feedback
59