Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 57

16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then select
the Debug Core Options tab in the Cell Properties window. Change
C_USER_SCAN_CHAIN* to 3
X-Ref Target - Figure 2-14
17. In the Project Manager, under Program and Debug, click Generate Bitstream
(Figure 2-15). A window pops up asking if it is ok to launch implementation. Click Yes.
X-Ref Target - Figure 2-15
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
(Figure 2-14). Click File > Save Constraints.
Figure 2-14: Debug Core Options for dbg_hub
Figure 2-15: Generate Bitstream
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Chapter 2: Creating the GTH IBERT Core
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