Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 65

5. In the new window select Tools > Run Tcl Script. In the Run Script window, navigate to
add_scm2.tcl in the extracted files and press OK. The SuperClock-2 Module Design
Sources and Constraints are added to the example design
X-Ref Target - Figure 3-6
6. The SuperClock-2 source code now needs to be added to the example IBERT wrapper.
Double-click ibert_7series_gtz_0_example in the Design Sources to open the verilog
code. Add the top level ports from top_scm2.v to the module declaration and
instantiate the top_scm2 module in the example IBERT wrapper
Save File.
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
Figure 3-6: Sources after Running add_scm2.tcl
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Chapter 3: Creating the GTZ IBERT Core
(Figure 3-6).
(Figure 3-7). Click File >
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