Creating The Gtx Ibert Core - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Chapter 1: VC7203 IBERT Getting Started Guide
Table 1-2: Si570 and Si5368 Frequency Table (Cont'd)
Address Protocol
101 Generic
102 Generic

Creating the GTX IBERT Core

Vivado Design Suite version 2013.2 or higher is required to rebuild the designs shown
here.
This section provides a procedure to create a single Quad GTX IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 113 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908).
1.
26
Frequency
Address
(MHz)
355.000 114
360.000 115
Start the Vivado Design Suite.
www.xilinx.com
Frequency
Protocol
(MHz)
Generic 420.000
Generic 425.000
VC7203 IBERT Getting Started Guide
Frequency
Address Protocol
(MHz)
127 Generic 485.000
UG847 (v3.0) July 10, 2013