Xilinx Virtex-7 FPGA VC7222 Getting Started Manual page 42

Viewing GTZ Transceiver Operation
After completing
demonstration is configured and running. The link status and test settings are displayed on
the Serial I/O Links tab in the Links Window shown in
Note the line rate and RX bit error count:
• The line rate for all GTZ transceivers is 28.05 Gb/s (see the Status Column in
Figure 1-33).
• Verify that there are no bit errors.
External or internal CTLE tuning might be required for successful GTZ operation. If the Link
Note:
No Link
Status shows
(Figure 1-33).
In the absence of a second BullsEye cable, using Internal CTLE puts the disconnected lanes in
Note:
loopback mode, while using External CTLE takes the lane out of loopback mode. If the BullsEye cable
is connected to Q300B, all Q300A lanes must be set in loopback mode. If the BullsEye cable is
connected to Q300B, all Q300A lanes must be set in loopback mode.
X-Ref Target - Figure 1-33
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
step 6, page 40 in Starting the SuperClock-2 Module, page
for one or more transceivers, click the respective lane
Figure 1-33: Serial I/O Analyzer Links
www.xilinx.com
Chapter 1: VC7222 IBERT Getting Started Guide
Figure 1-33.
36, the IBERT
CTLE Tune
button
42
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