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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
T#
Parameter
T16:
Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
T17:
Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Hold Time
T18:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Setup Time
T19:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Delay Time
T20:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Hold Time
NOTES:
1.
For a reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay
unless PWRGOOD is being driven inactive.
28
Table 14. Reset Conditions AC Specifications
Min
Max
4
2
20
1
5
2
20
Unit
Figure
BCLKs
Figure 18
BCLKs
Figure 18
ms
Figure 18
BCLKs
Figure 18
BCLKs
Figure 18
Figure 19
E
Notes
Before deassertion
of RESET#
After clock that
deasserts RESET#
Before deassertion
of RESET#
After assertion of
RESET#
1
After clock that
deasserts RESET#
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