Gtl+ Front Side Bus Specifications; Peci Dc Electrical Limits; Gtl+ Bus Resistance Definitions - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

Table 2-12. PECI DC Electrical Limits
Symbol
V
in
V
hysteresis
V
n
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
NOTES:
1. V supplies the PECI interface. PECI behavior does not affect V
TT
to Table 2-3
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
.
2.7.3.2

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 2-13. GTL+ Bus Resistance Definitions
Symbol
GTLREF_PU
GTLREF_PD
R
TT
COMP[3:0]
COMP8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable
GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected.
3. R
TT
4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to V
30
Definition and Conditions
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V = 0.75 * V )
OH TT
Low level output sink
(V = 0.25 * V )
OL TT
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
for V specifications.
TT
Table 2-7 for details on which GTL+ signals do not include on-die
Parameter
GTLREF pull up resistor
GTLREF pull down resistor
Termination Resistance
COMP Resistance
COMP Resistance
is the on-die termination resistance measured at V
.
SS
Min
-0.15
0.1 * V
TT
0.275 * V
TT
0.550 * V
TT
-6.0
0.5
N/A
TT
N/A
—
0.1 * V
TT
Table 2-13 lists the GTLREF specifications. The GTL+
Min Typ
57.6 * 0.99 57.6
100 * 0.99 100
45 50
49.40 49.90
24.65 24.90
TT
Electrical Specifications
Max Units Notes
V V
TT
— V
0.500 * V V
TT
0.725 * V V
TT
N/A mA
1.0 mA
50 µA
10 µA
10 pF
— V
p-p
min/max specifications. Refer
TT
Max Units Notes
57.6 * 1.01 Ω
100 * 1.01 Ω
55 Ω
50.40 Ω
25.15 Ω
/3 of the GTL+ output driver.
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