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Table 13.
PECI DC Electrical Limits
Symbol
V
in
V
hysteresis
V
n
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
NOTES:
1. V
supplies the PECI interface. PECI behavior does not affect V
TT
specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
.
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
26
Definition and Conditions
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V
= 0.75 * V
OH
TT)
Low level output sink
(V
= 0.25 * V
)
OL
TT
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above
300 MHz
Table 8
for details on which GTL+ signals do not include on-die
Table 14
Min
Max
-0.15
V
TT
0.1 * V
—
TT
0.275 * V
0.500 * V
TT
0.550 * V
0.725 * V
TT
-6.0
N/A
0.5
1.0
N/A
50
TT
N/A
10
N/A
10
0.1 * V
—
TT
min/max specifications. See
TT
lists the GTLREF specifications. The GTL+
Electrical Specifications
1
Units
Notes
V
2
V
V
TT
V
TT
mA
mA
3
µA
µA
3
pF
4
V
p-p
Table 4
for V
TT
Datasheet
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