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E
BCLK
RESET#
CRESET#
Ratio pins#
Using CRESET# (CMOS reset), the circuit in
Figure 10 can be used to share the pins. The pins of
the processors are bussed together to allow any one
of them to be the compatibility processor. The
component used as the multiplexer must not have
outputs that drive higher than 3.3 V in order to meet
the Pentium Pro processor's 3.3 V tolerant buffer
specifications. The multiplexer output current should
be limited to 200mA maximum, in case the V
supply to the processor ever fails.
The pull-down resistors between the multiplexer and
the processor (1KΩ) force a ratio of 2x into the
processor in the event that the Pentium Pro
processor powers up before the multiplexer and/or
the chip set. This prevents the processor from ever
seeing a ratio higher than the final ratio.
If the multiplexer were powered by V
would still be unknown until the 3.3 V supply came up
to power the CRESET# driver. A pull-down can be
used on CRESET# instead of the four between the
multiplexer and the Pentium Pro processor. In this
case, the multiplexer must be designed such that the
compatibility inputs are truly ignored as their state is
unknown.
PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
≤ Final
Ratio
Figure 9. Timing Diagram of Clock Ratio Signals
P
CC
P, CRESET#
CC
Final
Ratio
In any case, the compatibility inputs to the multiplexer
must meet the input specifications of the multiplexer.
This may require a level translation before the
multiplexer inputs unless the inputs and the signals
driving them are already compatible.
For FRC mode processors, one multiplexer will be
needed per FRC pair, and the multiplexer will need to
be clocked using BCLK to meet setup and hold times
to the processors. This may require the use of high
speed programmable logic.
3.5.2.
MIXING PROCESSORS OF
DIFFERENT FREQUENCIES
Mixing components of
frequencies is not fully supported and has not been
validated by Intel. One should also note when
attempting to mix processors rated at different
frequencies in a multiprocessor system that a
common bus clock frequency and a set of multipliers
must be found that is acceptable to all processors in
the system. Of course, a processor may be run at a
core frequency as low as its minimum rating.
Operating system support for multi-processing with
mixed frequency components should also be
considered.
Compatibility
different
internal
clock
15
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