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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
both processors. Also note the timing requirements
for PICCLK with respect to BCLK. With FRC
enabled,
PICCLK
must
Group Name
GTL+ Input
GTL+ Output
GTL+ I/O
3.3 V Tolerant Input
3.3 V Tolerant Output
Clock
4
4
APIC Clock
APIC I/O
4
JTAG Input
4
JTAG Output
4
Power/Other
5
NOTES:
1.
The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins after
the agent ID is determined.
2.
See PWRGOOD in Section 3.9.
3.
See THERMTRIP# in Section 3.10.
4.
These signals are tolerant to 3.3V. Use a 150Ω pull-up resistor on PICD[1:0] and 240Ω on TDO.
5.
CPUPRES# is a ground pin defined to allow a designer to detect the presence of a processor in a socket. (preliminary)
PLL1 and PLL2 are for decoupling the internal PLL (See Section 3.4.3.).
TESTHI pins should be tied to VCCP. A 10K pull-up may be used. See Section 3.11.
TESTLO pins should be tied to V
UP# is an open in the Pentium
V
P is the primary power supply.
CC
V
S is the secondary power supply used by some versions of the second level cache.
CC
V
5 is unused by Pentium Pro processor and is used by the OverDrive processor for fan/heatsink power. See
CC
Section 8.
VID[3:0] lines are described in Section 3.6.
V
[7:0] are the reference voltage pins for the GTL+ buffers.
REF
V
is ground.
SS
18
be
¼X
BCLK
and
Table 2. Signal Groups
1
BPRI#, BR[3:1]#
, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
PRDY#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#,
HITM#, LOCK#, REQ[4:0]#, RP#
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,
2
PWRGOOD
, SMI#, STPCLK#
FERR#, IERR#, THERMTRIP#
BCLK
PICCLK
PICD[1:0]
TCK, TDI, TMS, TRST#
TDO
CPUPRES#, PLL1, PLL2, TESTHI, TESTLO, UP#, V
VID[3:0], V
[7:0], V
REF
. A 1K pull-down may be used. See Section 3.11.
SS
®
Pro processor and tied to V
synchronized with respect to BCLK. PICCLK must
always lag BCLK by at least 1 ns and no more than
5 ns.
Signals
3
SS
in the OverDrive
®
processor (see Section 8.3.2 for usage).
SS
E
P, V
S, V
5,
CC
CC
CC
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