Super Io - ADLINK Technology COM Express Express-BL User Manual

Feature
SENFE
SECE
PME SCI
Hot Plug
PCIe Speed
Detect Non-Compiance
Extra Bus Reserved
Reseved Memory
Prefetchable Memory
Reserved I/O
PCIE LTR
PCIE LTR Lock
Snoop Latency Ocerrid
Non Snoop Latency Ocerrid
7.3.8.

Super IO

Feature
Super IO Chip
W83627DHG Super IO Configuration
Serial Port 1 Configuration
Serial Port
Device Settings
Change Settings
Options
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Auto
Gen1
Gen2
Disabled
Enable
0
10
10
4
Disabled
Enable
Disabled
Enable
Disabled
Manual
Auto
Disabled
Manual
Auto
Options
Info only
Info only
Enabled
Disabled
IO=3F8h; IRQ=4
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Description
Enable/Disable Root PCI Express System Error on Non-
Fatal Error.
Enable/Disable Root PCI Express System Error on
Correctable Error.
Enable/Disable PCI Express PME SCI.
Enable/Disable PCI Express Hot Plug.
Select PCI Express port speed.
Detect Non-Compliance PCI Express Device. If enabled, it
will take more time at POST time.
Extra Bus Reserved (0-7) for bridges behind this Root
Bridge.
Reserved Memory Range for this Root Bridge.
Prefetchable Memory Range for this Root Bridge.
Reserved I/O (4K/8K/12K/16K/.../48K) Range for this Root
Bridge.
PCIE Latency Reporting Enable/Disable.
PCIE LTR Configuration Lock.
Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerride for PCH PCIE.
Description
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Express-BL
Page 67