Ddr Signaling; Ddr Memory Expansion - Xilinx ML310 User Manual

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DDR Signaling

DDR Memory Expansion

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The FPGA DDR DIMM interface supports SSTL2 signaling. All DDR signals are controlled
impedance and are SSTL2 terminated.
The FPGA is capable of replicating up to three differential clock output pairs to the DIMM
in order to support either registered or unbuffered DIMMs. The ML310 DDR interface is
very flexible in the event different DDR memory is desired such as an unbuffered DIMM or
increased memory size. The DDR interface core delivered with EDK supports both
registered and unbuffered DRR Memory interfaces. Please review the EDK Processor IP
Reference Guide when migrating to a different DDR DIMM.
(U37)
CLKIN
CLK0
CLKFB
CLK90
DCM
CLKIN
CLKFB
Phase Shift
DCM
IBUFG
LVCMOS
25
DDR_CLK_FB_in
Figure 2-4: DDR DIMM Interface Block Diagram
Table 2-1 lists the connections from the FPGA to the DDR DIMM interface. Please note that
the DDR_DQ signal names do not correlate as the FPGA uses IBM notation, Big Endian,
while the DDR DIMMs use Intel notation, Little Endian.
Table 2-1: Connections from FPGA to DIMM Interface, P7
XC2VP30 Pin
UCF Signal Name
ddr_ad[0] AE23
ddr_ad[1] AJ23
Chapter 2: ML310 Embedded Development Platform
FDDRSE
D0
BUFG
D1
PLB_CLK
C0
C1
FDDRSE
CLK90_IN
D0
D1
BUFG
C0
C1
FDDRSE
D0
D1
C0
C1
BUFG
CLK0
DDR_CLK90_in
CLK90 C
CE
Q
BUFG
D
Schem Signal Name
(U37)
DDR_A0
DDR_A1
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DDR_CLK
SSTL2_I
DDR_CLK_N
SSTL2_I
DDR_CLK_FB_out
LVCMOS
25
ADDR
DDR Control
SSTL2_I
DDR_DQ/DQS
DQS_i
SSTL2_II
48
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ML310 User Guide
UG068 (v1.01) August 25, 2004
DDR DIMM (P7)
DIMM
(P7)