Gpio Led Interface; Gpio Lcd Interface - Xilinx ML310 User Manual

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GPIO LED Interface

GPIO LCD Interface

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All LEDs connected to the GPIO lines illuminate Green when driven with a logic zero and
extinguish with a logic one.
FPGA to the non-inverting buffer (U36).
Table 2-6: GPIO LED Connection from FPGA to U36
UCF Signal Name
DBG_LED_0 H13
DBG_LED_1 G13
DBG_LED_2 C10
DBG_LED_3 C11
DBG_LED_4 J14
DBG_LED_5 H14
DBG_LED_6 E14
DBG_LED_7 D14
The GPIO signals used to connect to the 16 pin LCD header (J13) are organized into two
types of I/O, output only and input/output. There are three output only signals and eight
input/output signals. The eight input/outputs are controlled by the logic level of the
FPGA_LCD_DIR signal. Driving FPGA_LCD_DIR to a logic one configures the LVCC3245
to drive the J13 connector while a logic zero configures the LVCC3245 to drive the
XC2VP30.
Table 2-7 shows the data bus signals on the GPIO LCD interface from the FPGA to U35.
Table 2-7: GPIO LCD Data Bus Connection from FPGA to U35
UCF Signal Name
FPGA_LCD_DB0 F19
FPGA_LCD_DB1 F20
FPGA_LCD_DB2 F17
FPGA_LCD_DB3 G17
FPGA_LCD_DB4 B21
FPGA_LCD_DB5 A21
FPGA_LCD_DB6 G18
FPGA_LCD_DB7 H18
FPGA_LCD_DIR C20
Chapter 2: ML310 Embedded Development Platform
Table 2-6 shows the connections for the GPIO LEDs from the
XC2VP30 Pin Schem Signal
(U37)
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7
XC2VP30 Pin Schem Signal
(U37)
FPGA_LCD_DB0
FPGA_LCD_DB1
FPGA_LCD_DB2
FPGA_LCD_DB3
FPGA_LCD_DB4
FPGA_LCD_DB5
FPGA_LCD_DB6
FPGA_LCD_DB7
FPGA_LCD_DIR
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LVC244 Buffer
Name (U36)
2
4
6
8
11
13
15
17
LVCC3245
Translator
Name
(U35)
3
4
5
6
7
8
9
10
2
ML310 User Guide
UG068 (v1.01) August 25, 2004
LED
DBG0
DBG1
DBG2
DBG3
DBG4
DBG5
DBG6
DBG7
LCD I/F
(J13)
7
8
9
10
11
12
13
14
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