Front Panel Interface Connector, J23 - Xilinx ML310 User Manual

Board Hardware

Front Panel Interface Connector, J23

ML310 User Guide
UG068 (v1.01) August 25, 2004
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SW3 = 0 0 0 (default)
SW3
ON
SYSACE CFG
CFGADDR[2:0] =
Figure 2-16: SW3 - SysACE CFG Switch Detail
The Front panel Interface connector (J23) is a 24-pin header that accepts a standard IDC 24
pin connector (0.1inch pitch). J23 provides an optional means to control and gather status
information from the ML310 board if it were to be enclosed similar to that of a desktop PC.
The functionality listed below can easily be connected via a user build cable that connects
to some collection of user created logic the could be used to control/monitor the
functionality available via the Front Panel Interface.
The front panel interface provides the following control capability available through the
J23 header.
♦
Power on/off the ML310
- ML310 board is delivered with a jumper installed on J23
♦
Select any of the eight System ACE configuration
- Connects to the 3 System ACE configuration address lines
♦
System ACE Reset
- Active low input
♦
CPU Reset
- Active low input
2.5V
System ACE
U38
Shown here with
CFGADDR[2:0]
RESET
set to "000".
ON => SW Closed
SYSACE_
RESET_N
0x0 0x1 0x2
Default
0x4 0x5 0x6
www.xilinx.com
1-800-255-7778
SW1
U31
Debounce
SYSACE
Reset
0x3
0x7
R
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