Ali South Bridge Interface, M1535D+, U15 - Xilinx ML310 User Manual

R

ALi South Bridge Interface, M1535D+, U15

40
All manuals and user guides at all-guides.com
Table 2-11 describes how the Primary PCI Bus interrupts are connected on the ML310
board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID
information.
Table 2-11: 3.3V Primary PCI Bus Information
Device
Device Name
PCI Slot 5 N/A
PCI Slot 3 N/A
U11, Enet Mac 0x1229
U15, ALI SB 0x1533
U15, ALi Pwr Mgt 0x7101
U15, ALI IDE 0x5299
U15, ALi Audio 0x5451
U15, Ali Modem 0x5457
U15, ALi USB#1 0x5237
U15, ALi USB#2 0x5237
U32, PCI-PCI Brg 0xAC23
U37, XC2VP30 0x0300
Table 2-12 describes how the Secondary PCI Bus interrupts are connected on the ML310
board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID
information.
Table 2-12: 5.0V Secondary PCI Bus Information
Device
Device Name
ID
PCI Slot 6 N/A
PCI Slot 4 N/A
U32, PCI-PCI Brg N/A
The ALi M1535D+ South Bridge augments the ML310 with many of the basic features
found on legacy Personal Computers (PCs). These basic PC features are only accessible
over the PCI Bus as this is the only way to access the ALI M1535D+. A brief description of
the ALi M1535D+ features employed on the ML310 board is discussed below. Please
review the ALi M1535D+ Data sheets, located on the ML310 CDROM, for more detailed
information.
Chapter 2: ML310 Embedded Development Platform
Vendor
Bus DEV IDSEL
ID ID
N/A 0
N/A 0
0x8086 0
0x10B9 0
0x10B9 0
0x10B9 0
0x10B9 0
0x10B9 0
0x10B9 0
0x10B9 0
0x104C 0
0x10EE 0
Vendor
Bus DEV IDSEL
ID
N/A 1
N/A 1
N/A N/A
www.xilinx.com
1-800-255-7778
FPGA
PCI
REQ
CLK
5 AD21 0 0
6 AD22 1 1
7 AD23 2 2
2 AD18 3 3
12 AD28 3 3
11 AD27 3 3
1 AD17 3 3
3 AD19 3 3
15 AD31 3 3
10 AD26 3 3
9 AD25 4 4
8 AD24 Int. 5
Bridge
REQ CLK
2 AD18 0 0
3 AD19 1 1
7 N/A Int. 4
ML310 User Guide
UG068 (v1.01) August 25, 2004
INTR
A,B,C,D
B,C,D,A
C
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
N/A
N/A
INTR
A,B,C,D
B,C,D,A
N/A