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Board Hardware
ML310 User Guide
UG068 (v1.01) August 25, 2004
All manuals and user guides at all-guides.com
Table 2-1: Connections from FPGA to DIMM Interface, P7
XC2VP30 Pin
UCF Signal Name
ddr_dq[32]
N27
ddr_dq[33]
P26
ddr_dq[34]
R25
ddr_dq[35]
R27
ddr_dq[36]
N28
ddr_dq[37]
P27
ddr_dq[38]
R26
ddr_dq[39]
R28
ddr_dq[40]
K27
ddr_dq[41]
L26
ddr_dq[42]
M27
ddr_dq[43]
N26
ddr_dq[44]
K28
ddr_dq[45]
L27
ddr_dq[46]
M28
ddr_dq[47]
N25
ddr_dq[48]
K25
ddr_dq[49]
K26
ddr_dq[50]
J27
ddr_dq[51]
J28
ddr_dq[52]
M25
ddr_dq[53]
M26
ddr_dq[54]
J25
ddr_dq[55]
J26
ddr_dq[56]
H28
ddr_dq[57]
G27
ddr_dq[58]
F28
ddr_dq[59]
E27
ddr_dq[60]
H27
ddr_dq[61]
G28
ddr_dq[62]
F27
ddr_dq[63]
E28
The connections from the FPGA to the DDR DIMM support either a registered or an
unbuffered DIMM. The only difference from a connectivity perspective is that the
Schem Signal Name
(U37)
DDR_DQ31
DDR_DQ30
DDR_DQ29
DDR_DQ28
DDR_DQ27
DDR_DQ26
DDR_DQ25
DDR_DQ24
DDR_DQ23
DDR_DQ22
DDR_DQ21
DDR_DQ20
DDR_DQ19
DDR_DQ18
DDR_DQ17
DDR_DQ16
DDR_DQ15
DDR_DQ14
DDR_DQ13
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ09
DDR_DQ08
DDR_DQ07
DDR_DQ06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ01
DDR_DQ00
www.xilinx.com
1-800-255-7778
R
DIMM
(P7)
133
131
127
126
40
39
35
33
123
121
117
114
31
28
24
23
110
109
106
105
20
19
13
12
99
98
95
94
8
6
4
2
25
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