Standa�D Type Tm Registe� Desc�Iption - Holtek HT66F20-1 Manual

Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as the three CCRP bits.
Name Bit 7
TM1C0 T1PAU
TM1C1 T1M1
TM1DL D7
TM1DH D15
TM1AL D7
TM1AH D15
TM1C0 Register
Bit 7
�a�e T1PAU
R/W R/W
POR 0
T1PAU: TM1 Counter Pause Control
Bit 7
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4 T1CK2, T1CK1, T1CK0: Select TM1 Counter clock
000: f
001: f
010: f
011: f
100: f
101: Undefined
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved
clock input will effectively disable the internal counter. The external pin clock source
can be chosen to be active on the rising or falling edge. The clock source f
system clock, while f
found in the oscillator section.
Bit 3 T1ON: TM1 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again. If the TM is in the Compare Match
Output Mode then the TM output pin will be reset to its initial condition, as specified
by the T1OC bit, when the T1ON bit changes from low to high.
Rev. 1.40
HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Bit 6 Bit 5 Bit 4
T1CK� T1CK1 T1CK0
T1M0 T1IO1 T1IO0
D� D5 D4
D14 D1� D1�
D� D5 D4
D14 D1� D1�
10-bit Standard TM Register List – HT66F20-1/HT68F20-1
6 5 4
T1CK� T1CK1 T1CK0
R/W R/W R/W
0 0 0
/4
SYS
SYS
/16
H
/64
H
TBC
and f are other internal clocks, the details of which can be
H TBC
94
Flash MCU with EEPROM
Bit 3 Bit 2 Bit 1
T1O� T1RP� T1RP1
T1OC T1POL T1DPX
D� D� D1
D11 D10 D9
D� D� D1
D11 D10 D9
3 2 1
T1O� T1RP� T1RP1
R/W R/W R/W
0 0 0
�ove��e� ��� �01�
Bit 0
T1RP0
T1CCLR
D0
D8
D0
D8
0
T1RP0
R/W
0
is the
SYS