Co�Pact Type Tm Ope�Ating Modes; Co�Pa�E Match Output Mode - Holtek HT66F20-1 Manual

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
Bit 3 T0OC: TP
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the TM
whether TM
It has no effect if the TM
Output Mode it determines the logic level of he TM0 output pin before a compare
match occurs. In the PWM Mode it determines if the PWM signal is active high or
active low.
T0POL: TP0_0, TP0_1 Output polarity Control
Bit 2
0: Non-invert
1: Invert
This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set
high the TM0 output pin will be inverted and not inverted when the bit is zero. It has
no effect if the TM0 is in the Timer/Counter Mode.
Bit 1 T0DPX: TM0 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
T0CCLR: Select TM0 Counter clear condition
Bit 0
0: TM0 Comparator P match
1: TM0 Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM0 contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not
used in the PWM Mode.
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the T0M1 and T0M0
bits in the TM0C1 register.
Compare Match Output Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register, should be set to "00" respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the T0CCLR bit is low, there are two ways in which the counter can be cleared. One is when a
compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both T0AF and T0PF interrupt request flags for the Comparator A and
Comparator P respectively, will both be generated.
Rev. 1.40
_0, TP _1 Output control bit
0 0
is being used in the Compare Match Output Mode or in the PWM Mode.
0
is in the Timer/Counter Mode. In the Compare Match
0
87
output pin. Its operation depends upon
0
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