Holtek HT66F20-1 Manual page 85

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
TM0C0 Register
Bit 7
�a�e T0PAU
R/W R/W
POR 0
T0PAU: TM0 Counter Pause Control
Bit 7
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4 T0CK2~T0CK0: Select TM0 Counter clock
000: f
001: f
010: f
011: f
100: f
101: Undefined
110: TCK0 rising edge clock
111: TCK0 falling edge clock
These three bits are used to select the clock source for the TM0. Selecting the
Reserved clock input will effectively disable the internal counter. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
f
SYS
can be found in the oscillator section.
T0ON: TM0 Counter On/Off Control
Bit 3
0: Off
1: On
This bit controls the overall on/off function of the TM0. Setting the bit high enables
the counter to run, clearing the bit disables the TM0. Clearing this bit to zero will
stop the counter from counting and turn off the TM0 which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value. If the TM0 is in the Compare Match Output
Mode then the TM0 output pin will be reset to its initial condition, as specified by the
T0OC bit, when the T0ON bit changes from low to high.
Bit 2~0 T0RP2~T0RP0: TM0 CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM0 clocks
001: 128 TM0 clocks
010: 256 TM0 clocks
011: 384 TM0 clocks
100: 512 TM0 clocks
101: 640 TM0 clocks
110: 768 TM0 clocks
111: 896 TM0 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter's highest three bits. The result of this
comparison can be selected to clear the internal counter if the T0CCLR bit is set to
zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.40
6 5
T0CK� T0CK1 T0CK0
R/W R/W R/W
0 0
/4
SYS
SYS
/16
H
/64
H
TBC
is the system clock, while f and f
H
85
4 3 2
T0O� T0RP� T0RP1
R/W R/W
0 0 0
are other internal clocks, the details of which
TBC
�ove��e� ��� �01�
1 0
T0RP0
R/W R/W
0 0