Eeprom Data Memory - Holtek HT66F20-1 Manual

STATUS Register
Bit 7
�a�e —
R/W —
POR —
Bit 7, 6 Unimplemented, read as "0"
Bit 5 TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred.
Bit 4 PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3 OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
Z: Zero flag
Bit 2
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
Bit 1
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
Bit 0 C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
C is also affected by a rotate through carry instruction.

EEPROM Data Memory

All devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 64×8 bits. Unlike the Program Memory and RAM
Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is
therefore not directly addressable in the same way as the other types of memory. Read and Write
operations to the EEPROM are carried out in single byte operations using an address and data
register in Bank 0 and a single control register in Bank 1.
HT��F�0-1/HT�8F�0-1
HT��F�0-1/HT�8F�0-1
Rev. 1.40
HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
6 5
— TO PDF
— R
— 0
highest-order bit or vice versa.
from the high nibble into the low nibble in subtraction
not take place during a subtraction operation
Device Capacity
�8
Flash MCU with EEPROM
4 3 2
OV Z
R R/W R/W
0 x x
Address
��×8 00H~1FH
�4×8 00H~�FH
�ove��e� ��� �01�
1 0
AC C
R/W R/W
x x
" x" unknown