Enhanced Type Tm Registe� Desc�Iption - Holtek HT66F20-1 Manual

Enhanced Type TM Register Description
Overall operation of the Enhanced TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which
setup the different operating and control modes as well as the three CCRP bits.
Name Bit7
TM1C0 T1PAU
TM1C1 T1AM1
TM1C� T1BM1
TM1DL D7
TM1DH —
TM1AL D7
TM1AH —
TM1BL D7
TM1BH —
TM1C0 Register – 10-bit ETM
Bit 7
�a�e T1PAU
R/W R/W
POR 0
Bit 7 T1PAU: TM1 Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
T1CK2~T1CK0: Select TM1 Counter clock
Bit 6~4
000: f
001: f
010: f
011: f
100: f
101: Reserved
110: TCK1 rising edge clock
111: TCK1 falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved
clock input will effectively disable the internal counter. The external pin clock source
can be chosen to be active on the rising or falling edge. The clock source f
system clock, while f
found in the oscillator section.
Rev. 1.40
HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Bit6 Bit5 Bit4
T1CK� T1CK1 T1CK0
T1AM0 T1AIO1 T1AIO0
T1BM0 T1BIO1 T1BIO0
D� D5 D4
— — —
D� D5 D4
— — —
D� D5 D4
— — —
10-bit Enhanced TM Register List – HT66F30-1/HT68F30-1
6 5 4
T1CK� T1CK1 T1CK0
R/W R/W R/W
0 0 0
/4
SYS
SYS
/16
H
/64
H
TBC
and f are other internal clocks, the details of which can be
H TBC
108
Flash MCU with EEPROM
Bit3 Bit2 Bit1
T1O� T1RP� T1RP1
T1AOC T1PAOL T1CD�
T1BOC T1PBOL T1PWM1 T1PWM0
D� D� D1
— — D9
D� D� D1
— — D9
D� D� D1
— — D9
3 2 1
T1O� T1RP� T1RP1
R/W R/W R/W
0 0 0
�ove��e� ��� �01�
Bit0
T1RP0
T1CCLR
D0
D8
D0
D8
D0
D8
0
T1RP0
R/W
0
is the
SYS