Holtek HT66F20-1 Manual page 56

Entering the SLEEP1 Mode
There is only one way for these devices to enter the SLEEP1 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the
WDT or LVD on. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the
f clock.
SUB
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT clock source is selected to come from
the f clock as the WDT is enabled.
SUB
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for these devices to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the
FSYSON bit in WDTC register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction, but the Time Base clock and f
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT clock source is selected to come from
the f clock and the WDT is enabled. The WDT will stop if its clock source originates from the
SUB
system clock.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for these devices to enter the IDLE1 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the
FSYSON bit in WDTC register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock and Time Base clock and f
stop at the "HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT
clock source which originates from the f
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.40
HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
clock will be on.
SUB
clock will be on and the application program will
SUB
clock or from the system clock.
SUB
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