I � C Inte�Face - Holtek HT66F20-1 Manual

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
I C Interface
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The I C interface is used to communicate with external peripheral devices such as sensors,
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EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I C Interface Operation
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The I C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
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many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I
will be transmitted and received on the I
When two devices communicate with each other on the bidirectional I
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I
mode and the slave receive mode.
H T X B i t
D i r e c t i o n C o n t r o l
S C L P i n
D a t a i n L S B
S D A P i n
D a t a O u t M S B
M
U
E n a b l e / D i s a b l e A c k n o w l e d g e
X
There are several configuration options associated with the I
the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration
option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no
effect. A configuration option exists to allow a clock other than the system clock to drive the I
interface. Another configuration option determines the debounce time of the I
the internal clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I
Rev. 1.40
D e v i c e D e v i c e
S l a v e M a s t e r
I C Master Slave Bus Connection
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C bus is identified by a unique address which
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C bus.
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I C D a t a R e g i s t e r S l a v e A d d r e s s R e g i s t e r
2
( S I M D ) ( S I M A )
A d d r e s s
C o m p a r a t o r
S h i f t R e g i s t e r
R e a d / w r i t e S l a v e
8 - b i t D a t a C o m p l e t e
T r a n s m i t / R e c e i v e
D e t e c t S t a r t o r S t o p
C o n t r o l U n i t
I C Block Diagram
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151
V D D
S D A
S C L
D e v i c e
S l a v e
C bus, one is known as the
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C bus, the slave transmit
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D a t a B u s
A d d r e s s M a t c h
H A A S B i t I C I n t e r r u p t
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S R W B i t
H C F B i t
H B B B i t
C interface. One of these is to enable
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C interface. This uses
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C data transfer speed, there
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C
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