Ti�E�/Counte� Mode; Pwm Output Mode - Holtek HT66F20-1 Manual

Timer/Counter Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.

PWM Output Mode

To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 10 respectively.
The PWM function within the TM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but
of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the T0CCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the T0DPX bit in the TM0C1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The T0OC bit in the TM0C1 register is used to
select the required polarity of the PWM waveform while the two T0IO1 and T0IO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The T0POL bit is
used to reverse the polarity of the PWM output waveform.
CTM, PWM Mode, Edge-aligned Mode, T0DPX=0
CCRP 001b
Pe�iod 1�8
Duty
If f =16MHz, TM clock source is f
SYS
The CTM PWM output frequency=(f
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
CTM, PWM Mode, Edge-aligned Mode, T0DPX=1
CCRP 001b
Pe�iod
Duty 1�8
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value.
Rev. 1.40
HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
010b 011b 100b
�5� �84 51�
CCRA
/4, CCRP=100b and CCRA=128,
SYS
/4)/512=f /2048=7.8125 kHz, duty=128/512=25%.
SYS SYS
010b 011b 100b
CCRA
�5� �84 51�
90
Flash MCU with EEPROM
101b 110b 111b
�40 7�8 89�
101b 110b 111b
�40 7�8 89�
�ove��e� ��� �01�
000b
10�4
000b
10�4