Holtek HT66F20-1 Manual page 111

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
T1AOC: TP1A Output control bit
Bit 3
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the TM
output pin before a compare match occurs. In the PWM Mode it determines if the
PWM signal is active high or active low.
Bit 2 T1APOL: TP1A Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1A output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1 T1CDN: TM1 Count up or down flag
0: Count up
1: Count down
Bit 0 T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparatror P match
1: TM1 Comparatror A match
This bit is used to select the method which clears the counter. Remember that
the Enhanced TM contains three comparators, Comparator A, Comparator B and
Comparator P, but only Comparator A or Comparator P can be selected to clear the
internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will
be cleared when a compare match occurs from the Comparator P or with a counter
overflow. A counter overflow clearing method can only be implemented if the CCRP
bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or
Input Capture Mode.
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