A/D Ope�Ation - Holtek HT66F20-1 Manual

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1
Flash MCU with EEPROM
ACERL Register
Bit 7
�a�e ACE7
R/W R/W
POR 1
ACE7: Define PA7 is A/D input or not
Bit 7
0: Not A/D input
1: A/D input, AN7
ACE6: Define PA6 is A/D input or not
Bit 6
0: Not A/D input
1: A/D input, AN6
ACE5: Define PA5 is A/D input or not
Bit 5
0: Not A/D input
1: A/D input, AN5
ACE4: Define PA4 is A/D input or not
Bit 4
0: Not A/D input
1: A/D input, AN4
ACE3: Define PA3 is A/D input or not
Bit 3
0: Not A/D input
1: A/D input, AN3
ACE2: Define PA2 is A/D input or not
Bit 2
0: Not A/D input
1: A/D input, AN2
ACE1: Define PA1 is A/D input or not
Bit 1
0: Not A/D input
1: A/D input, AN1
ACE0: Define PA0 is A/D input or not
Bit 0
0: Not A/D input
1: A/D input, AN0
A/D Operation
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to "0" by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
to be either f
SYS
ADCK2~ADCK0 bits in the ADCR1 register.
Rev. 1.40
6 5
ACE� ACE5 ACE4
R/W R/W
1 1
or a subdivided version of f
1�5
4 3 2
ACE� ACE�
R/W R/W R/W
1 1 1
. The division ratio value is determined by the
SYS
1 0
ACE1 ACE0
R/W R/W
1 1
, can be chosen
SYS
�ove��e� ��� �01�