Programming/Fpga Configuration - Lattice Semiconductor LatticeSC PCI Express x1 User Manual

Lattice Semiconductor
Table 1. Board Power Supply Fuses (see Appendix A, Figure 6)
Table 2. Board Power Supply Indicators (see Appendix A, Figure 6)
Table 3. Board Supply Disconnects (see Appendix A, Figure 7)
PCI Express Power Interface
Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power
from a PCI Express host board.
VCC Core Selection
(see Appendix A, Figure 6)
The VCC core can be selected on the board to be either 1.0V or 1.2V using J7.
A jumper shunt placed between pin 1 and pin 2 will connect 1.0V. A jumper shunt between pin 2 and pin 3 will con-
nect 1.2V.
Programming/FPGA Configuration
(see Appendix A, Figure 5)
A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and render the
board inoperable.
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An ispDOWNLOAD Cable is included with this board and also with each ispLEVER
may also be purchased separately from Lattice.
F1 1.0V/1.2V Core Fuse
F2 1.5V Fuse
F3 3.3V Fuse
F4 1.2V Fuse
F5 2.5V Fuse
F6 1.8V Fuse
D6 2.5V Source Good Indicator
D7 3.3V Source Good Indicator
D8 1.0V/1.2V VCC Core Source Good Indicator
D9 1.5V Source Good Indicator
D10 1.8V Source Good Indicator
D11 1.2V Source Good Indicator
D12 12V Input Good Indicator
Screw Terminal for 12V DC
TB1 Pin 1 (Square PCB Pad) = 12V DC
Pin 2 = Ground
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LatticeSC PCI Express x1
Evaluation Board User's Guide
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design tool shipment. Cables