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Lattice Semiconductor ispClock5400D User Manual

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ispClock5400D Evaluation Board
User's Guide
July 2010
Revision: EB50_01.2

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Summary of Contents for Lattice Semiconductor ispClock5400D

  • Page 1  ispClock5400D Evaluation Board  User’s Guide July 2010 Revision: EB50_01.2...
  • Page 2 Introduction Thank you for choosing the Lattice Semiconductor ispClock™ device family! This guide describes how to start using the ispClock5400D Evaluation Board, an easy-to-use platform for evaluat- ing and designing with the ispClock5406D in-system-programmable differential clock distribution device. The evalu- ation board can be used stand-alone to review the performance and in-system programmability of the ispClock5406D device or as a companion board and clock source for LatticeECP3™...

  • Page 3: Software Requirements

    For a complete list of the various connections and interfaces used on the ispClock5400D Evaluation Board, please refer to the schematics in Appendix A.

  • Page 4: Hardware Requirements

    To monitor clock outputs: 1. If you have not done so already, see the Programming the ispClock5400D Evaluation Board with ispVM section of this document for details on set-up for the programming cable and applying power to the evaluation board.
  • Page 5 Evaluation Board Lattice Semiconductor User’s Guide 2. Set DIP switches SW1 3 and 4 ON and all other switches OFF. The blue LOCK LED lights to indicate the on-chip PLL is stable and locked to a reference clock. 3. Start PAC-Designer.
  • Page 6 Evaluation Board Lattice Semiconductor User’s Guide 9. If the board is not programmed with the demo project yet, press the Download icon on the top toolbar. Figure 4. PAC-Designer Top Toolbar The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
  • Page 7 Evaluation Board Lattice Semiconductor User’s Guide Figure 6. Scope Plot - Four Differential Outputs Note: For user-designed boards and other applications, refer to the data sheet configurations and the schematics of Appendix A. The schematic shows different resistor combinations for the different output bank settings. In LVDS mode the schematic uses a single 100 Ohm resistor between each BANK_P and BANK_N pin as a fully differential output.
  • Page 8 Evaluation Board Lattice Semiconductor User’s Guide Figure 7. Scope Plot - Bank 0 and Bank 2 Overlapped Note that a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps. 2. In PAC-Designer choose Tools > Design Utilities…...
  • Page 9 Evaluation Board Lattice Semiconductor User’s Guide 4. Position the mouse over the rising edge of the Bank2 Time waveform. The cursor will changes to a double-arrow icon to indicate a waveform edit. 5. Click and hold the Bank 2 Time waveform, then drag it three units to the right....
  • Page 10 Evaluation Board Lattice Semiconductor User’s Guide Invert Clock Output This section describes the procedure to invert the ispClock5406D output. In this procedure you will use the ispClock5406D Invert feature to invert Bank2 output. To invert a clock output: 1. From the PAC-Designer schematic view, double-click the BANK_2+/BANK_2- Output Block....
  • Page 11 Evaluation Board Lattice Semiconductor User’s Guide Figure 11. Scope Plot - Inverted Output Bank 6. Repeat steps 1-4 to adjust the output bank to not invert the output (Inverted = No) and reprogram the device. Modify Clock Phase Skew This section describes the procedure to modify phase skew of the ispClock5406D output.
  • Page 12 Evaluation Board Lattice Semiconductor User’s Guide Figure 12. Scope Plot - Phase Skew Adjustment The waveform shows the BANK_2 output advanced 1.24 ns. Modify the Reference Clock Source Input The evaluation board provides both 100 MHz (REFA) and 156.25 MHz (REFB) reference clock sources using on- board CMOS oscillators.
  • Page 13 Evaluation Board Lattice Semiconductor User’s Guide  Figure 13. Scope Plot - 156.25 MHz Output The 156.25 MHz clock from the REFB input output appears on the scope. 6. Toggle position 3 of the DIP switch (USER3) on the evaluation board back to the 1=REF-SEL position to enable the 100 MHz input reference clock, REFA_P/N input.
  • Page 14 Evaluation Board Lattice Semiconductor User’s Guide Figure 14. Design Utilities Dialog Box 6. Select ispClock_5406_I2C_Utility.exe and click OK. The ispClock5406D I C Utility appears. Figure 15. ispClock5406D I C Utility 7. Choose Options > I2C Interface… The Cable and I/O Port Setup Dialog appears.
  • Page 15 Evaluation Board Lattice Semiconductor User’s Guide 8. Click the Change… button until the Uses PC USB Port title appears. 9. Disable the Bypass Hardware Checking (Demo Mode) option. 10. Click the Settings… button. The USB Settings dialog appears. 11. From the Select USB port name… section, choose Search for download cable on all USB ports and click Connect Now....
  • Page 16 Evaluation Board Lattice Semiconductor User’s Guide Figure 17. Scope Plot - Skew Measurement Note a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps. 3. From the ispClock5406D I C Utility click the Output Group 1 button....
  • Page 17 Evaluation Board Lattice Semiconductor User’s Guide - Ref Select, reference A or B MUX control - Phase–Skew value, 16 values - Output Delay Mode for Zero-Delay mode or FOB, Fan-Out Buffer mode 4. Double-click the Bank 2 output block (0x0, 8 TUD, 0=Disable) of the schematic....
  • Page 18 C utility or modify the PAC-Designer project then reprogram the device. Period Jitter Measurement The demo consists of setting up the ispClock5400D Evaluation Board hardware and a Wavecrest (Gigamax) SIA- 3000D analyzer to demonstrate the ultra-low phase jitter of the ispClock5406D device.
  • Page 19 Evaluation Board Lattice Semiconductor User’s Guide 5. Specify REF Frequency: 100 then click the Internal Feedback, Modify... button. The External Feedback Setting dialog appears. 6. Select Internal Feedback, select Feedback taken from V-Divider 8, and click OK. 7. From the PLL Core Settings dialog, click OK.

  • Page 20: Download Demo Designs

    Use the procedure below to re-export a JEDEC programming file for any ispClock5406D demo project for the eval- uation board. 1. Install and license PAC-Designer software (www.latticesemi.com/products/designsoftware/pacdesigner). 2. Download the demo source files from the ispClock5400D Evaluation Board web page. 3. Run PAC-Designer. 4. Open the <demo>.pac project file.
  • Page 21 Connecting Programming Cable and a Power Source To connect the ispClock5400D Evaluation Board to your PC: 1. Plug the ispDOWNLOAD Cable into the USB port on the PC.
  • Page 22 Evaluation Board Lattice Semiconductor User’s Guide Figure 21. Change Programming Cable Interface Dialog Box 4. From the Programming Cable Interface list, select Uses PC USB and click OK. The Cable and I/O Port Setup dialog appears. Figure 22. Cable and I/O Port Setup Dialog Box 5.
  • Page 23 Figure 24. PAC-Designer JTAG Prompt 7. Click OK to dismiss the message. 8. Close PAC-Designer. Programming the Evaluation Board To repgrogram the ispClock5400D Evaluation Board: 1. Run PAC-Designer. 2. Open the <demo>.pac project file. 3. Choose Tools > Download The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.

  • Page 24: Dip Switch

    4. Click OK. PAC-Designer reprograms the evaluation board with the updated JEDEC programming file. ispClock5400D Evaluation Board This section describes the features of the ispClock5400D Evaluation Board in detail. The features appear in alpha- betical order. DIP Switch To simplify the use of the evaluation board an 8-position DIP switch (SW1) is provided for common adjustments.
  • Page 25 (J1), then zero ohm resistors must be used for R14 and R12, and R15, R9, R7, and R5 should be removed. On-Board Termination The ispClock5400D Evaluation Board is designed to support a variety of on-board termination schemes. The board comes from the factory with zero-ohm jumpers in place of the on-board termination in order to support off-board termination and quick validation of designs with an oscilloscope.
  • Page 26 Evaluation Board Lattice Semiconductor User’s Guide Figure 27. Bank 0 MLVDS with On-Board Termination Scope ispClock BANK_0P On Board T-Line SMA to BNC Cable 50 ohms / 64.3 mm 50 ohms / 91 cm 0.1uF MLVDS Buffers On Board T-Line SMA to BNC Cable 0.1uF...
  • Page 27 Evaluation Board Lattice Semiconductor User’s Guide Figure 29. Bank 0 SSTL15/SSTL18 with On Board Termination VCCO ispClock Scope BANK_0P On Board T-Line SMA to BNC Cable 50 ohms / 64.3 mm 50 ohms / 91 cm 71.5 18.7 45.3...

  • Page 28: Power Supply Connections

    Evaluation Board Lattice Semiconductor User’s Guide HCSL HCSL termination involves a bias network to ground at the driver and no termination at the end of the T-Line. Figure 32 shows the drivers biased through series resistors R16 and R17 (value of 33 ohms) combined with resis- tors R19 and R20 (value of 50 ohms).

  • Page 29: Environmental Requirements

    Evaluation Board Lattice Semiconductor User’s Guide ispClock_5400_I2C_OutGroup_Sch.emf ispClock_5400_I2C_PLL_Sch.emf 5. Rerun the ispClock5406D I C Utility. Environmental Requirements The evaluation board must be stored between -40°C and 100°C. The recommended operating temperature is between 0°C and 55°C. The evaluation board can be damaged without proper anti-static handling.

  • Page 30: Ordering Information

    The following documentation is recommended for evaluation and demonstrations: • AN6080: Using a Low-Cost CMOS Oscillator as a Reference Clock for SERDES Applications • AN6081: Driving SERDES Devices with the ispClock5400D Differential Clock Buffer • EB44: LatticeECP3 Serial Protocol Board User’s Guide • EB39: LatticeECP3 Video Protocol Board User’s Guide...

  • Page 31: Technical Support Assistance

    Evaluation Board Lattice Semiconductor User’s Guide Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary December 2009 01.0 Initial release. December 2009 01.1 Added Troubleshooting section. July 2010 01.2...

  • Page 32: Appendix A. Schematic

    Evaluation Board Lattice Semiconductor User’s Guide Appendix A. Schematic Figure 33. ispClock5406D...
  • Page 33 Evaluation Board Lattice Semiconductor User’s Guide Figure 34. ispClock5406D Reference Oscillator “A”...
  • Page 34 Evaluation Board Lattice Semiconductor User’s Guide Figure 35. ispClock5406D Reference Oscillator “B”...
  • Page 35 Evaluation Board Lattice Semiconductor User’s Guide Figure 36. ispClock5406D Output Bank 0 Termination and Connectors...
  • Page 36 Evaluation Board Lattice Semiconductor User’s Guide Figure 37. ispClock5406D Output Bank 2 Termination and Connectors...
  • Page 37 Evaluation Board Lattice Semiconductor User’s Guide Figure 38. ispClock5406D Output Bank 3 Termination and Connectors...
  • Page 38 Evaluation Board Lattice Semiconductor User’s Guide Figure 39. ispClock5406D Output Bank 5 Termination and Connectors...
  • Page 39 Evaluation Board Lattice Semiconductor User’s Guide Figure 40. +12V to +5V Input 3.3V VCC Output and VCCO Adjustable...
  • Page 40 Evaluation Board Lattice Semiconductor User’s Guide Figure 41. Test, JTAG and I C Interface and Connectors...

  • Page 41: Appendix B. Bill Of Materials

    Evaluation Board Lattice Semiconductor User’s Guide Appendix B. Bill of Materials Table 3. Bill of Materials Item Quantity Reference Part Part Number C13, C12, C15, C18, C21, C24, 0.1uF SMD 0805 ceramic capacitor C0805C104K5RACTU C26, C30-31, C35-45, C46, C47 C4, C7 1.0 uF SMD 0805...
  • Page 42 Evaluation Board Lattice Semiconductor User’s Guide Table 3. Bill of Materials (Continued) Item Quantity Reference Part Part Number Q1, Q2 NPN Trans. SOT-23 MMBT2369A NPN Trans. SOT-223 FZT649TA ispPAC-CLK5406D 3.3V fixed regulator SMD 8SOIC TPS77733D Adj LDO Regulator SMD 8SOIC...

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Pacclk5406d-s-evn

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